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3M employee and church chorister Art Fry needed something to temporarily mark pages in his hymnal. He was in luck because his colleague, Spencer Silver, accidentally developed a glue that was too weak for other purposes. After initially discouraging consumer response, Post-it Notes became a hit in 1979.
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| Number | Title | Issue Date |
| 7427544 | Semiconductor device and method of manufacturing the same A semiconductor device includes an element isolation insulating film provided in a semiconductor substrate between first and second element regions, a gate electrode running over the element isolation insulating film, first and second element regions, a first stoppe... | 09/23/2008 |
| 7420280 | Reduced stress under bump metallization structure An improved under bump structure for use in semiconductor devices is described. The under bump structure includes a passivation layer having a plurality of vias. The vias are positioned such that a plurality of vias are associated with (i.e., located over) each cont... | 09/02/2008 |
| 7413975 | Interconnect substrate, semiconductor device, methods of manufacturing the same, circuit board, and electronic equipment A first conductive layer is formed. An insulating layer is formed so that at least a part of the insulating layer is disposed on the first conductive layer. A second conductive layer is formed so that at least a part of the second conductive layer is disposed on the... | 08/19/2008 |
| 7397073 | Barrier dielectric stack for seam protection The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal ... | 07/08/2008 |
| 7381642 | Top layers of metal for integrated circuits The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used... | 06/03/2008 |
| 7365025 | Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having ... | 04/29/2008 |
| 7339204 | Backside contact for touchchip A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a ... | 03/04/2008 |
| 7326632 | Method for fabricating metal wirings of semiconductor device A method for fabricating metal wirings of a semiconductor including forming an etch stop layer on a semiconductor substrate, and forming an inter metal dielectric on the etch stop layer. The method also includes forming a via hole in the inter metal dielectric so as... | 02/05/2008 |
| 7320934 | Method of forming a contact in a flash memory device A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric laye... | 01/22/2008 |
| 7300862 | Method for manufacturing semiconductor device High quality dielectric layers may be achieved without introducing excessive impurities when a semiconductor device is manufactured by a method that includes forming a lower wire layer on a structure above a semiconductor substrate, forming a silicon rich oxide laye... | 11/27/2007 |
| 7291532 | Low resistance contact in a semiconductor device In a method for manufacturing a contact electrically contacting an electrically conductive silicon structure, a substrate with a surface is provided, the substrate having the silicon structure at the surface. Silicon oxide is grown selectively on at least part of th... | 11/06/2007 |
| 7259056 | Method for manufacturing semiconductor device In a method for manufacturing a semiconductor device, gate insulation films and gate electrodes are first formed on a substrate. An impurity is implanted into each gate electrode. Next, a first heat treatment is performed to the substrate for diffusing the impurity ... | 08/21/2007 |
| 7247947 | Semiconductor device comprising a plurality of semiconductor constructs A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper lay... | 07/24/2007 |
| 7247552 | Integrated circuit having structural support for a flip-chip interconnect pad and method therefor A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increas... | 07/24/2007 |
| 7229873 | Process for manufacturing dual work function metal gates in a microelectronics device The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stack... | 06/12/2007 |
| 7205223 | Method of forming an interconnect structure for a semiconductor device A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer passivates the copper layer surface and enhances the thermal conductivity of a semiconductor substrate by... | 04/17/2007 |
| 7192859 | Method of manufacturing semiconductor device and display device To provide a method of forming a wiring for the purpose of providing a semiconductor device, which is superior in reliability and cost performance. Further, to provide methods of manufacturing a semiconductor device and a display device by using the method of formin... | 03/20/2007 |
| 7186639 | Metal interconnection lines of semiconductor devices and methods of forming the same Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being des... | 03/06/2007 |
| 7157372 | Coaxial through chip connection A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing the annulus trench with a metal, etching a via trench within the periphery of the ann... | 01/02/2007 |
| 7094687 | Reduced dry etching lag A method of forming via structures between a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is formed, and a dielectric layer is formed over the first electrically conductive layer. A first pho... | 08/22/2006 |
| 6696732 | Semiconductor device having S/D to S/D connection and isolation region between two semiconductor elements A plurality of MOS type FET devices 14 and 16 are provided on a semiconductor substrate 12. A lower interlayer insulating film 20 is provided thereon. Each of through holes 22, which extends from each of gate electrodes 14c of the plural FET devices via s... | 02/24/2004 |
| 6689654 | Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region an... | 02/10/2004 |
| 6656853 | Enhanced deposition control in fabricating devices in a semiconductor wafer A method for an enhanced deposition control includes forming a transistor on a substrate of a semiconductor wafer, and depositing a silicon nitride layer on the transistor and the substrate in a reactor at a pressure of at least approximately 104 | 12/02/2003 |
| 6653194 | Method for forming contact hole in semiconductor device Disclosed is a method for forming a contact hole in the process of manufacturing a logic device employing a shallow trench isolation (STI) method. The method prevents an isolation region from being damaged because there is little overlap margin for a cont... | 11/25/2003 |
| 6649500 | Semiconductor device including an insulated gate field effect transistor and method of manufacturing the same A semiconductor device is disclosed including an IGFET (insulated gate field effect transistor) and a method of manufacturing the same. The semiconductor device may include an oxide film (115) or a nitride film (106) provided on a side surface of a gate e... | 11/18/2003 |
| 6642582 | Circuit structure with a parasitic transistor having high threshold voltage A circuit structure integrated in a semiconductor substrate comprises at least one pair of transistors each being formed each in a respective active area region and having a source region and a drain region, as well as a channel region intervening between... | 11/04/2003 |
| 6642114 | Semiconductor device and method for fabricating the same A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insula... | 11/04/2003 |
| 6638827 | Semiconductor device and method of manufacturing it To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed... | 10/28/2003 |
| 6630718 | Transistor gate and local interconnect A method of forming a local interconnect for a semiconductor integrated circuit, the local interconnect comprising a refractory silicide contact having a substantially small sheet resistance formed at an exhumed surface of a gate stack, wherein the local ... | 10/07/2003 |
| 6576963 | Semiconductor device having transistor A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the e... | 06/10/2003 |
| 6559489 | Semiconductor device and method of manufacturing the same A semiconductor device capable of a high-speed operation is provided. The semiconductor device is provided with low concentration impurity regions, a gate electrode formed with gate oxide film interposed between the gate electrode and a silicon substrate,... | 05/06/2003 |
| 6555915 | Integrated circuit having interconnect to a substrate and method therefor A contact between a source/drain and a gate is made by making a selected portion of the gate dielectric conductive by an implant into that selected portion of the gate dielectric. The gate material is in a layer over the entire integrated circuit. Areas w... | 04/29/2003 |
| 6555450 | Contact forming method for semiconductor device A contact forming method of a semiconductor device is disclosed, in which a pad polysilicon layer is formed at an active region of a cell array, thereafter an upper portion of a gate is opened when a spacer of a NMOS transistor region is formed. And at th... | 04/29/2003 |
| 6551901 | Method for preventing borderless contact to well leakage An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semicondu... | 04/22/2003 |
| 6548871 | Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process,... | 04/15/2003 |
| 6548845 | Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate, a gate electrode formed over the semiconductor substrate and a first interlevel insulating layer which is formed over the semiconductor substrate and has first and second contact holes defined by ... | 04/15/2003 |
| 6534807 | Local interconnect junction on insulator (JOI) structure A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, ... | 03/18/2003 |
| 6518151 | Dual layer hard mask for eDRAM gate etch process A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and usi... | 02/11/2003 |
| 6512299 | Semiconductor device and a manufacturing process therefor This invention provides a semiconductor device comprising gate insulating films 13, 21 formed on the main surface of a silicon substrate 11; gate electrodes 14, 22 consisting of polycrystalline silicon; and a high-density doped layer 17, wherein a part of... | 01/28/2003 |
| 6503795 | Method for fabricating a semiconductor device having a storage cell The present invention discloses a method for fabricating a semiconductor device. In an open bit line cell aligned local interconnection type device having a minimum line width of 1F and a pattern interval of 1F, hard masks are formed on respective conduct... | 01/07/2003 |
