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| Number | Title | Issue Date |
| 7439124 | Method of manufacturing a semiconductor device and semiconductor device Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by ... | 10/21/2008 |
| 7435683 | Apparatus and method for selectively recessing spacers on multi-gate devices Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed. ... | 10/14/2008 |
| 7432120 | Method for realizing a hosting structure of nanometric elements Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the b... | 10/07/2008 |
| 7410872 | Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure A method for sealing electronic devices formed on a semiconductor substrate includes forming a plurality of first electronic devices adjacent a first portion of the semiconductor substrate, with each first electronic device including a first region comprising at lea... | 08/12/2008 |
| 7405119 | Structure and method for a sidewall SONOS memory device A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a... | 07/29/2008 |
| 7399663 | Embedded strain layer in thin SOI transistors and a method of forming the same By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded s... | 07/15/2008 |
| 7399690 | Methods of fabricating semiconductor devices and structures thereof Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece and at least one feature disposed over the workpiece. A first spacer is d... | 07/15/2008 |
| 7387921 | Method of manufacturing semiconductor device Disclosed is a method of manufacturing a semiconductor device, comprising forming a gate electrode on a main surface of a semiconductor substrate via a gate insulating film, laminating sequentially a first insulating film with oxidation resistance and a silicon film... | 06/17/2008 |
| 7361587 | Semiconductor contact and nitride spacer formation system and method The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate conn... | 04/22/2008 |
| 7358128 | Method for manufacturing a transistor A semiconductor device and a method for manufacturing the same is disclosed, in which a spacer containing nitrogen therein has a tensile stress and enables device reliability improvement by improving the On-current without regard to the kind of transistor. The semic... | 04/15/2008 |
| 7354837 | Fabrication method for single and dual gate spacers on a semiconductor device A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the ... | 04/08/2008 |
| 7354839 | Gate structure and a transistor having asymmetric spacer elements and methods of forming the same Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and exte... | 04/08/2008 |
| 7338872 | Method of depositing a layer of a material on a substrate The present invention makes it possible to precisely deposit a material adjacent a feature on a substrate. A layer of the material is deposited on the substrate. The layer is planarized and exposed to an etchant. The etchant is adapted to selectively remove the mate... | 03/04/2008 |
| 7309633 | Semiconductor device including MOS field effect transistor having offset spacers or gate sidewall films on either side of gate electrode and method of manufacturing the same First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity d... | 12/18/2007 |
| 7306996 | Methods of fabricating a semiconductor device having a metal gate pattern A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer st... | 12/11/2007 |
| 7303962 | Fabricating method of CMOS and MOS device A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substr... | 12/04/2007 |
| 7294581 | Method for fabricating silicon nitride spacer structures Embodiments of methods for fabricating a spacer structure on a semiconductor substrate are provided herein. In one embodiment, a method for fabricating a spacer structure on a semiconductor substrate includes providing a substrate containing a base structure over wh... | 11/13/2007 |
| 7291895 | Integrated circuitry A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the s... | 11/06/2007 |
| 7271049 | Method of forming self-aligned low-k gate cap A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be signi... | 09/18/2007 |
| 7268393 | Semiconductor devices and methods of manufacturing the same Semiconductor devices and methods of manufacturing semiconductor devices which achieve higher integration and higher operating speed are provided. A disclosed example semiconductor device includes a semiconductor substrate of a first conductivity type; a gate insula... | 09/11/2007 |
| 7256095 | High voltage metal-oxide-semiconductor transistor devices and method of making the same A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polys... | 08/14/2007 |
| 7244642 | Method to obtain fully silicided gate electrodes The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255 | 07/17/2007 |
| 7230296 | Self-aligned low-k gate cap A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be signi... | 06/12/2007 |
| 7208361 | Replacement gate process for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a polysilicon layer on a dielectric layer, which is formed on a substrate. The polysilicon layer is etched to generate a patterned polysilicon layer with an upper surface that is ... | 04/24/2007 |
| 7189617 | Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the requi... | 03/13/2007 |
| 7176084 | Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielect... | 02/13/2007 |
| 7169676 | Semiconductor devices and methods for forming the same including contacting gate to source Semiconductors having electrically coupled gate and impurity doped regions and methods for fabricating the same are provided. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and an impurity doped re... | 01/30/2007 |
| 7148113 | Semiconductor device and fabricating method thereof A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the subs... | 12/12/2006 |
| 7132353 | Boron diffusion barrier by nitrogen incorporation in spacer dielectrics A method of forming a sidewall spacer on a gate electrode is described. The method includes generating a first plasma from a silicon containing precursor and oxide precursor, and forming a silicon oxy-nitride layer on the sidewall of the gate electrode. The method a... | 11/07/2006 |
| 7132704 | Transistor sidewall spacer stress modulation A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode (116) over a gate dielectric (104) over a semiconductor substrate (102). A spacer film (124) exhibiting a tensile stress characteris... | 11/07/2006 |
| 7132368 | Method for repairing plasma damage after spacer formation for integrated circuit devices A method for processing integrated circuit memory devices. The method includes supporting a partially completed substrate, the substrate comprising a plurality of MOS gate structures. Each of the gate structures has substantially vertical regions that define sides o... | 11/07/2006 |
| 7112497 | Multi-layer reducible sidewall process The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors c... | 09/26/2006 |
| 7109550 | Semiconductor fabrication process with asymmetrical conductive spacers A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that ... | 09/19/2006 |
| 7101741 | Dual double gate transistor and method for forming The present invention provides a dual gate transistor and a method for forming the same that results in improved device performance and density. The present invention uses a double gate design to implement a dual gate transistor. A double gate is a gate which is for... | 09/05/2006 |
| 7098098 | Methods for transistors formation using selective gate implantation Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a... | 08/29/2006 |
| 7094636 | Method of forming a conductive line A method of forming a conductive line includes forming conductive material received over a semiconductor substrate into a line having opposing sidewalls. Insulative material is deposited over the line, and is planarized. An insulating spacer forming layer is deposit... | 08/22/2006 |
| 7091549 | Programmable memory devices supported by semiconductor substrates The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tun... | 08/15/2006 |
| 7091567 | Semiconductor device including air gap between semiconductor substrate and L-shaped spacer and method of fabricating the same A semiconductor device includes source/drain regions, a gate pattern disposed on the semiconductor substrate between the source/drain regions, and L-shaped spacers that are used as masks in the forming of the source/drain regions. The L-shaped spacers each include a... | 08/15/2006 |
| 7078287 | Method of manufacturing semiconductor device A gate electrode is formed on a silicon substrate. First spacers are formed on side surfaces of the gate electrode. With the gate electrode and the first spacers as masks, the surface of the silicon substrate is chipped off to form steplike portions at positions adj... | 07/18/2006 |
| 6894357 | Gate stack for high performance sub-micron CMOS devices A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectr... | 05/17/2005 |
