Class 257/E21.625 - With particular manufacturing method of gate insulating layer, e.g., different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.616. This subclass
No. of patents: 260
Last issue date: 10/14/2008

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Number	Title	Issue Date
6124171	Method of forming gate oxide having dual thickness by oxidation process Transistors are formed on the substrate having two different thickness' of gate oxides. A silicon nitride mask is used to protect one of the gate oxides while the other is grown. A nitride mask is formed from a hydrogen balanced nitride layer formed using...	09/26/2000
6110842	Method of forming multiple gate oxide thicknesses using high density plasma nitridation A method for forming integrated circuits having multiple gate oxide thicknesses. A high density plasma is used for selective plasma nitridation to reduce the effective gate dielectric thickness in selected areas only. In one embodiment, a pattern (12) is ...	08/29/2000
6110782	Method to combine high voltage device and salicide process A method for integrating salicide and high voltage device processes in the fabrication of high and low voltage devices on a single wafer is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating a low vol...	08/29/2000
6096664	Method of manufacturing semiconductor structures including a pair of MOSFETs A method for forming a pair of MOSFETs in different electrically isolated regions of a silicon substrate. Each one of the MOSFETs has a different gate oxide thickness. A first layer of silicon dioxide is grown to a predetermined thickness over the surface...	08/01/2000
6093661	Integrated circuitry and semiconductor processing method of forming field effect transistors In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area ...	07/25/2000
6093659	Selective area halogen doping to achieve dual gate oxide thickness on a wafer A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A pattern (36) is then formed exposing areas of the circuit where a thinner gate oxide (20) is...	07/25/2000
6091109	Semiconductor device having different gate oxide thicknesses by implanting halogens in one region and nitrogen in the second region The present invention provides a structure comprising: a first oxide film having a first thickness and extending on a first region of a semiconductor substrate; and a second oxide film having a second thickness which is thicker than the first thickness of...	07/18/2000
6087236	Integrated circuit with multiple gate dielectric structures An integrated circuit includes insulated gate field effect transistors (IGFETs), having gate dielectric layers wherein a nitrogen concentration in the gate dielectric varies between a first concentration at the gate electrode/gate dielectric interface and...	07/11/2000
6075273	Integrated circuit device in which gate oxide thickness is selected to control plasma damage during device fabrication An integrated circuit device in which the gate oxide of the devices in the integrated circuit device is selected to control plasma damage during device processing is disclosed. The integrated circuit device has at least two transistors, each transistor ha...	06/13/2000
6071775	Methods for forming peripheral circuits including high voltage transistors with LDD structures A peripheral circuit for a nonvolatile integrated circuit memory device includes a semiconductor substrate with a well region having a first conductivity type adjacent a face of the substrate. A first transistor on the well region includes a first gate in...	06/06/2000
6063670	Gate fabrication processes for split-gate transistors A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A first gate dielectric (20) is formed. Next, a disposable layer (22) is formed over the first...	05/16/2000
6064102	Semiconductor device having gate electrodes with different gate insulators and fabrication thereof A semiconductor device having gate electrodes with different gate insulators and a process for fabricating such device is provided. Consistent with one embodiment of the invention, a semiconductor device is provided in which a first gate insulator is form...	05/16/2000
6051510	Method of using a hard mask to grow dielectrics with varying characteristics A method of employing an ambient diffusion barrier to isolate a first dielectric on a silicon substrate against further growth during formation of a second dielectric on the silicon substrate. Subsequent to formation of the diffusion barrier, an exposed s...	04/18/2000
6046474	Field effect transistors having tapered gate electrodes for providing high breakdown voltage capability and methods of forming same Field effect transistors having tapered gate electrodes include a body region of first conductivity type extending to a surface of a semiconductor substrate. Source and drain regions of second conductivity type are formed in the substrate and a gate elect...	04/04/2000
6037201	Method for manufacturing mixed-mode devices A method for manufacturing mixed-mode devices that can eliminate watermarks resulting from the formation of residues at the dead corner space of an inverted trapezium-shaped structure at the upper end of a shallow trench during dual gate-oxide processing ...	03/14/2000
6037224	Method for growing dual oxide thickness using nitrided oxides for oxidation suppression A method for growing dual thickness oxide includes the step of forming a first oxide having a first thickness. A thin layer of the first oxide is transformed into an oxygen diffusion barrier, wherein the oxygen diffusion barrier interfaces at the silicon ...	03/14/2000
6033958	Method of fabricating dual voltage MOS transistors A method of forming dual voltage MOS transistors includes first forming a mask layer, covering one of the at least two device regions and exposing another one of the two device regions. A gate oxide layer is then formed by thermal oxidation on the exposed...	03/07/2000
6033998	Method of forming variable thickness gate dielectrics Provided is a method of fabricating gate dielectric layers having variable thicknesses and compositions over different regions of a semiconductor wafer. In a preferred embodiment of the present invention, a gate oxide layer is first grown over the various...	03/07/2000
6030872	Method of fabricating mixed-mode device A method for fabricating a mixed-mode device. A first gate oxide layer and a second gate oxide layer are formed. The polysilicon layer is used as a mask to pattern the gate oxide layers. Additionally, a top electrode is formed during the first gate oxide ...	02/29/2000
6025234	Method for manufacturing thick gate oxide device A method for forming devices having a thick gate oxide. The method comprises the steps of providing a substrate having different device areas already defined thereon through shallow trench isolation, then forming a first gate oxide layer over the substrat...	02/15/2000
6015732	Dual gate oxide process with increased reliability Within a dual gate oxide process, gate oxide is formed within regions on a substrate. Gate material, such as polysilicon, is placed over a first region. The gate material extends over field oxide surrounding the first region. Gate oxide within a second re...	01/18/2000
5989962	Semiconductor device having dual gate and method of formation The invention comprises a method of forming a semiconductor device is provided where a first gate insulator layer 26 is formed on an outer surface of semiconductor substrate 24. A mask body 28 is formed to cover portions of the insulator layer 26. The exp...	11/23/1999
5985706	Polishing method for thin gates dielectric in semiconductor process A semiconductor process in which an initial gate dielectric layer is formed on an upper surface of a semiconductor substrate. The initial gate dielectric layer is polished with a chemical mechanical polish to produce a finished gate dielectric layer. A th...	11/16/1999
5970345	Method of forming an integrated circuit having both low voltage and high voltage MOS transistors The invention comprises an integrated circuit having both low voltage and high voltage MOS transistors and a method for making the integrated circuit. In accordance with the method of making the integrated circuit, a first oxide layer is formed outwardly ...	10/19/1999
5960289	Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region A method for forming a dual gate oxide (DGO) structure begins by forming a first oxide layer (106) within active areas (110) and (112). A protection layer (108a) is then formed over the layer (106). A mask (114) is used to allow removal of the layers (106...	09/28/1999
5933731	Semiconductor device having gate oxide films having different thicknesses and manufacturing method thereof The element separation region has a section on its surface, where the first resist pattern and second resist pattern overlap with each other. The overlapping section is not etched even while removing the dummy oxide films formed in the first and second re...	08/03/1999
5926708	Method for providing multiple gate oxide thicknesses on the same wafer The present invention is directed to a method of manufacturing an integrated circuit with two or more gate oxide thicknesses on the same wafer. The method includes the steps of growing a first oxide layer on a substrate, depositing a first polysilicon lay...	07/20/1999
5926729	Method for forming gate oxide layers of various predefined thicknesses A method is provided for use in semiconductor fabrication processes for forming a plurality of gate oxide layers with various predefined thicknesses in mixed-mode or embedded circuits that are formed in a semiconductor substrate. In particular, the gate o...	07/20/1999
5918116	Process for forming gate oxides possessing different thicknesses on a semiconductor substrate Gate oxides having different thicknesses are grown on a semiconductor layer by the process which comprises forming a semiconductor layer on a substrate, growing an oxide layer on the semiconductor layer, exposing a selected area of the oxide layer, amorph...	06/29/1999
5907777	Method for forming field effect transistors having different threshold voltages and devices formed thereby The preferred embodiment provides a method for fabricating field effect transistors that have different threshold voltages without requiring excessive masking and other fabrication steps. In particular, the method facilitates the formation of FETs with di...	05/25/1999
5904575	Method and apparatus incorporating nitrogen selectively for differential oxide growth A method for forming an oxide on the surface of a semiconductor substrate. The method includes the steps of: placing the semiconductor substrate in an atmosphere containing an atmosphere of an oxide growth inhibiting compound; applying laser energy to at ...	05/18/1999
5905283	Method of forming a MOS transistor having gate insulators of different thicknesses The semiconductor device includes (A) a first MOS transistor including (a) a main surface at a part of which recesses are formed, an inner surface of the recesses defining a crystal plane being able to be thermally oxidized at higher speed than the main s...	05/18/1999
5874772	Semiconductor device A semiconductor device is obtained in which initial breakdown voltage of an insulating film is improved. On a silicon substrate, an insulating film is provided which is not more than 100 Å in thickness. An electrode is provided on the silicon substrate, ...	02/23/1999
5834352	Methods of forming integrated circuits containing high and low voltage field effect transistors therein Methods of forming integrated circuits containing high and low voltage insulated-gate field effect transistors (IGFET) include the steps of forming first and second insulating layers having unequal thicknesses at first and second locations on a face of a ...	11/10/1998
5817570	Semiconductor structure for an MOS transistor and method for fabricating the semiconductor structure The MOS transistor has field plates and a subarea of the gate formed from the same polysilicon layer. A gate oxide lying underneath them is produced at the beginning of the fabrication process and it therefore exhibits particularly high quality. The polys...	10/06/1998
5811336	Method of forming MOS transistors having gate insulators of different thicknesses The semiconductor device includes (A) a first MOS transistor including (a) a main surface at a part of which recesses are formed, an inner surface of the recesses defining a crystal plane being able to be thermally oxidized at higher speed than the main s...	09/22/1998
5786252	Method of manufacturing a semiconductor device, and semiconductor device manufactured by such a method A deep diffusion of the back-gate region provided in a self-aligned manner with respect to the gate electrode is necessary in a DMOS transistor for obtaining a sufficiently high punch-through voltage between source and drain. The combination of a comparat...	07/28/1998
5716863	Method of manufacturing semiconductor device having elements different in gate oxide thickness and resistive elements A plurality of device isolation insulating layers are formed on the surface of a semiconductor substrate. A gate insulating layer is formed on the substrate surface between each device isolation insulating layer. After that, a first polysilicon layer is d...	02/10/1998
5677208	Method for making FET having reduced oxidation inductive stacking fault An improved manufacturing method for a semiconductor device, which can reduce process inductive fault such as oxidation inductive stacking fault (OSF) and contribute to the improvement of the electric characteristics of the semiconductor device, is disclo...	10/14/1997
5672521	Method of forming multiple gate oxide thicknesses on a wafer substrate An integrated circuit device and manufacturing process wherein a first region is formed in a substrate with a dopant that enhances oxide formation and a second region is formed in the substrate with a dose of nitrogen that retards oxide formation. An oxid...	09/30/1997

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Class 257/E21.625 - With particular manufacturing method of gate insulating layer, e.g., different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants (EPO)