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| Number | Title | Issue Date |
| 7422944 | Semiconductor device A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first cir... | 09/09/2008 |
| 7387955 | Field effect transistor and method for manufacturing the same A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and... | 06/17/2008 |
| 7375015 | Manufacturing method which prevents abnormal gate oxidation A method for manufacturing a gate electrode structure for preventing abnormal oxidation of a refractory metal due to an oxidation process, includes forming an insulating film on a surface of a semiconductor substrate; forming an impurity diffused polysilicon film on... | 05/20/2008 |
| 7374989 | Flash memory and methods of fabricating the same Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed withi... | 05/20/2008 |
| 7354848 | Poly-silicon-germanium gate stack and method for forming the same A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that c... | 04/08/2008 |
| 7341906 | Method of manufacturing sidewall spacers on a memory device, and device comprising same The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device compri... | 03/11/2008 |
| 7332775 | Protruding spacers for self-aligned contacts A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous c... | 02/19/2008 |
| 7306990 | Information storage element, manufacturing method thereof, and memory array An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavi... | 12/11/2007 |
| 7273783 | Methods for reducing void formation in semiconductor devices A method of forming a semiconductor device includes forming an insulating layer on a semiconductor substrate. The insulating layer has a trench therein with opposing sidewalls and a bottom surface. A first conductive layer is formed on the sidewalls and on the botto... | 09/25/2007 |
| 7157378 | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on... | 01/02/2007 |
| 6894357 | Gate stack for high performance sub-micron CMOS devices A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectr... | 05/17/2005 |
| 6703312 | Method of forming active devices of different gatelengths using lithographic printed gate images of same length As disclosed herein, a method is provided for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in a second portion such as an array portion of an integra... | 03/09/2004 |
| 6674137 | Semiconductor device and its manufacturing method A semiconductor device is disclosed that can include a gate electrode (6) having a lower layer (6a) and a higher layer (6b), a mask insulating film (7) formed over a higher layer (6b). A side surface insulating film (9) may be formed on sides of a gate el... | 01/06/2004 |
| 6653686 | Structure and method of controlling short-channel effect of very short channel MOSFET A semiconductor device comprising a gate having an approximately 0.05 μm channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the ... | 11/25/2003 |
| 6617085 | Wet etch reduction of gate widths A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a desired gate length and etching the etch-control layer and the h... | 09/09/2003 |
| 6613621 | Methods of forming self-aligned contact pads using a damascene gate process Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the ... | 09/02/2003 |
| 6600195 | Semiconductor device A semiconductor device capable of preventing variations in threshold voltage and having high reliability is provided. The semiconductor device includes a semiconductor substrate having a semiconductor region, and a field-effect transistor. The field-effec... | 07/29/2003 |
| 6579757 | Method for fabricating semiconductor device which prevents gates of a peripheral region from being oxidized A method of fabricating a semiconductor device, includes the steps of forming gates in a cell region and in a peripheral region of a substrate, forming a polysilicon layer over an entire surface of the resultant structure, partially removing portions of t... | 06/17/2003 |
| 6552402 | Composite MOS transistor device A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second group... | 04/22/2003 |
| 6548359 | Asymmetrical devices for short gate length performance with disposable sidewall An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of th... | 04/15/2003 |
| 6548872 | Integrated circuitry comprising multiple transistors with different channel lengths A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openin... | 04/15/2003 |
| 6541357 | Semiconductor device and method of manufacturing the same There is disclosed a semiconductor device having: a semiconductor substrate; a first gate electrode constructed of a multi-layered stack member provided in a memory region, formed with memory cells, of a surface area of the semiconductor substrate so that... | 04/01/2003 |
| 6509243 | Method for integrating high-voltage device and low-voltage device In a method for integrating a high-voltage device and a low-voltage device, a substrate includes a first isolation region separating a high-voltage device region and a low-voltage device region, a second isolation region formed in a scribe region, and a p... | 01/21/2003 |
| 6376292 | Self-aligning photolithography and method of fabricating semiconductor device using the same Self-aligning photolithography method and a method of fabricating a semiconductor device using the same, in which the photolithography method is performed using a lower pattern without employing a separate mask. The self-aligning photolithography method i... | 04/23/2002 |
| 6300199 | Method of defining at least two different field effect transistor channel lengths using differently angled sidewall segments of a channel defining layer A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openin... | 10/09/2001 |
| 6281558 | Semiconductor device and manufacturing method thereof A high-voltage element (H)to which a high gate voltage is applied, and a low-voltage element (L) to which a low gate voltage is applied, are formed in a semiconductor substrate (1). Bird's beaks (8, 18) are formed in gate insulating films (7, 17) by therm... | 08/28/2001 |
| 6271092 | Method for fabricating a semiconductor device A method for fabricating a semiconductor device of the present invention comprises steps of forming a first oxide layer on a semiconductor substrate comprising a memory cell unit and an input/output circuit unit, removing selectively the first oxide layer... | 08/07/2001 |
| 6238982 | Multiple threshold voltage semiconductor device fabrication technology An integrated circuit process technology for simultaneously forming multiple threshold voltage devices is disclosed. Devices having both high speed and low power consumption can be fabricated for use in integrated circuits having a need for both, such as ... | 05/29/2001 |
| 6204129 | Method for producing a high-voltage and low-voltage MOS transistor with salicide structure A method for producing self-aligned silicidation, substantially facilitating the integration of the high-voltage and low-voltage MOS device, is disclosed. The method includes providing, the present invention provides a integration of high-voltage and low-... | 03/20/2001 |
| 6198140 | Semiconductor device including several transistors and method of manufacturing the same In a semiconductor device including high-voltage, middle-voltage, and low voltage transistors having operating voltages different from one another, a gate length and a thickness of a gate oxide film are increased as the operating voltage is increased. Acc... | 03/06/2001 |
| 6187619 | Method to fabricate short-channel MOSFETs with an improvement in ESD resistance A method to fabricate simultaneously a MOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The ESD protective devices are fabricated with a double diffused drain (DDD) junction. In the functional region, a MOSFET structure... | 02/13/2001 |
| 6171893 | Method for forming self-aligned silicided MOS transistors with ESD protection improvement The method of forming MOS transistors includes the following steps. First, isolation regions are formed in the semiconductor substrate to separate the semiconductor substrate into an ESD protective region and a functional region. A gate insulator layer is... | 01/09/2001 |
| 6156605 | Method of fabricating DRAM device A DRAM device having a triple well structure and a manufacturing method of the device are disclosed. The DRAM device includes first and second well regions of a first conductivity type formed in a semiconductor substrate of the first conductivity type. Th... | 12/05/2000 |
| 6121090 | Self-aligned silicided MOS devices with an extended S/D junction and an ESD protection circuit A method for fabricating simultaneously a self-aligned silicided and an ESD protective transistor is disclosed. To improve operation speed, the MOS transistor is manufactured with an extended S/D junction; however, there is no salicide and LDD and, with a... | 09/19/2000 |
| 6111298 | Etch stop layer formed within a multi-layered gate conductor to provide for reduction of channel length A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of tra... | 08/29/2000 |
| 6077736 | Method of fabricating a semiconductor device A method of fabricating a semiconductor device includes the steps of preparing a semiconductor substrate having a first region and a second region, forming a first gate electrode and a second gate electrode over the semiconductor substrate at the first an... | 06/20/2000 |
| 6057199 | Method of producing a semiconductor body The process produces a semiconductor body with a first region that has a self-aligning structure and with a further second region. The insulation layer lying on a semiconductor layer in the first region is fully removed in the second region using a photog... | 05/02/2000 |
| 6040220 | Asymmetrical transistor formed from a gate conductor of unequal thickness An asymmetrical transistor, and a gate conductor used in forming that transistor, are provided. The gate conductor is formed by removing upper portions of the gate conductor along an elongated axis which the gate conductor extends. The removed portions pr... | 03/21/2000 |
| 6025253 | Differential poly-edge oxidation for stable SRAM cells An SRAM cell having improved stability includes pass transistors having gate electrodes which are shaped by oxidation so that the lower edges of the gate electrodes are raised away from the substrate surface. Because the gate electrodes of the load and pu... | 02/15/2000 |
| 6022769 | Method of making self-aligned silicided MOS transistor with ESD protection improvement An isolation region is formed in a semiconductor substrate for separating a functional region and a ESD protective region. A gate structure and lightly doped active region is formed. An insulator layer is formed and a portion of the layer is removed for a... | 02/08/2000 |
