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| Number | Title | Issue Date |
| 7435652 | Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite diff... | 10/14/2008 |
| 7432164 | Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second ... | 10/07/2008 |
| 7416949 | Fabrication of transistors with a fully silicided gate electrode and channel strain Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer of the first gate, and first substrate portions adjacent to the first ... | 08/26/2008 |
| 7384830 | Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric fo... | 06/10/2008 |
| 7382023 | Fully depleted SOI multiple threshold voltage application An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A se... | 06/03/2008 |
| 7368372 | Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, t... | 05/06/2008 |
| 7341900 | Semiconductor device and method for manufacturing the same A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and... | 03/11/2008 |
| 7341916 | Self-aligned nanometer-level transistor defined without lithography A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates form... | 03/11/2008 |
| 7332420 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semicon... | 02/19/2008 |
| 7312126 | Process for producing a layer arrangement, and layer arrangement for use as a dual gate field-effect transistor The invention relates to a process for producing a layer arrangement, in which, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate, a first semiconductor layer is formed on the sacrificial layer, a first electrically insulating layer is ... | 12/25/2007 |
| 7306996 | Methods of fabricating a semiconductor device having a metal gate pattern A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer st... | 12/11/2007 |
| 7306990 | Information storage element, manufacturing method thereof, and memory array An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavi... | 12/11/2007 |
| 7282403 | Temperature stable metal nitride gate electrode An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is charact... | 10/16/2007 |
| 7268064 | Method of forming polysilicon layer in semiconductor device Disclosed herein is a method of forming a polysilicon film of a semiconductor device. Upon deposition process of a polysilicon film, the inflow of a gas is reduced to 150 sccm to 250 sccm to control abnormal deposition depending upon excessive inflow of the gas. Acc... | 09/11/2007 |
| 7265423 | Technique for fabricating logic elements using multiple gate layers Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and mem... | 09/04/2007 |
| 7259070 | Semiconductor devices and methods for fabricating the same Disclosed are semiconductor devices and methods for fabricating the same. According to one embodiment, the method includes sequentially forming a gate insulation layer and a conductive layer on a semiconductor substrate. A buried impurity region is then formed in th... | 08/21/2007 |
| 7256078 | High mobility plane FinFETs with equal drive strength An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. Th... | 08/14/2007 |
| 7229873 | Process for manufacturing dual work function metal gates in a microelectronics device The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stack... | 06/12/2007 |
| 7183168 | Method of manufacturing a semiconductor device having a silicide film A method of manufacturing a semiconductor device includes implanting germanium ions into a selected portion of a semiconductor region containing at least silicon, forming P-type and N-type diffusion layers in the semiconductor region, and forming a suicide film whic... | 02/27/2007 |
| 7145207 | Gate structure of semiconductor memory device A gate structure of a semiconductor memory device capable of preventing a poly void generation by forming a hard mask and maintaining a hysteresis area within a certain value. The gate structure of the semiconductor memory device includes: a gate insulation layer fo... | 12/05/2006 |
| 7091077 | Method of directionally trimming polysilicon width Polysilicon or other material is directionally trimmed using two layers of photoresist and a photoresist etching process, such as ashing. A first layer of photoresist is patterned on a wafer. Portions of the first patterned photoresist are covered with a second laye... | 08/15/2006 |
| 6696333 | Method of making integrated circuit with MOSFETs having bi-layer metal gate electrodes A method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes, removing the gate electrodes of the first composition, and repla... | 02/24/2004 |
| 6693313 | Field effect transistors, field effect transistor assemblies, and integrated circuitry The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a... | 02/17/2004 |
| 6686617 | Semiconductor chip having both compact memory and high performance logic A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory regi... | 02/03/2004 |
| 6686276 | Semiconductor chip having both polycide and salicide gates and methods for making same A semiconductor process is provided that creates transistors having polycide gates in a first region of a semiconductor substrate and transistors having salicide gates in a second region of the semiconductor substrate. A polysilicon layer having a first p... | 02/03/2004 |
| 6667199 | Semiconductor device having a replacement gate type field effect transistor and its manufacturing method The present invention provides a MISFET with a replacement gate electrode, which ensures large ON-current. A semiconductor device, in which on the substrate, first and second field effect transistors are formed, the first field effect transistor is a repl... | 12/23/2003 |
| 6627971 | Polysilicon structures with different resistance values for gate electrodes, resistors, and capacitor plates A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the substrate. A hard masking layer is formed over the silicon oxide ... | 09/30/2003 |
| 6627963 | Method for fabricating a merged integrated circuit device The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the ... | 09/30/2003 |
| 6613624 | Method for fabricating an integrated semiconductor circuit Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel region by an altered work function of the electrons. Transistors in semiconductor circuits havin... | 09/02/2003 |
| 6593633 | Method and device for improved salicide resistance on polysilicon gates The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Anothe... | 07/15/2003 |
| 6586289 | Anti-spacer structure for improved gate activation A method and structure for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a structure having a plurality of patterned g... | 07/01/2003 |
| 6559059 | Method for fabricating a MOS transistor of an embedded memory The present invention provides a method of manufacturing a MOS transistor of an embedded memory. The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of the semiconductor wafer and t... | 05/06/2003 |
| 6552377 | Mos transistor with dual metal gate structure A method for making a ULSI MOSFET includes depositing a high-k gate insulator on a silicon substrate and then depositing a field oxide layer over the gate insulator. The field oxide layer is masked with photoresist and the photoresist patterned to establi... | 04/22/2003 |
| 6548870 | Semiconductor device In the semiconductor device, a first impurity region and a second impurity region are formed in a surface of a semiconductor substrate at a regular interval, and a gate insulating layer is formed on the semiconductor substrate between the first impurity r... | 04/15/2003 |
| 6531365 | Anti-spacer structure for self-aligned independent gate implantation A method for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a plurality of patterned gate stacks atop a layer of gate d... | 03/11/2003 |
| 6521964 | Device having spacers for improved salicide resistance on polysilicon gates A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a ... | 02/18/2003 |
| 6514824 | Semiconductor device with a pair of transistors having dual work function gate electrodes Techniques are described for fabricating a pair of ଲ-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. ... | 02/04/2003 |
| 6509223 | Method for making an embedded memory MOS The present invention provides a method for forming an embedded memory MOS. The method involves first forming a first dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array ar... | 01/21/2003 |
| 6509618 | Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a ... | 01/21/2003 |
| 6509235 | Method for making an embedded memory MOS The present invention provides a method for forming an embedded memory MOS. The method involves first forming a dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array area and... | 01/21/2003 |
