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| Number | Title | Issue Date |
| 7422960 | Method of forming gate arrays on a partial SOI substrate The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. Th... | 09/09/2008 |
| 7416931 | Methods for fabricating a stress enhanced MOS circuit Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed material to form a stressed dummy gate electrode overlying a channel ... | 08/26/2008 |
| 7405130 | Method of manufacturing a semiconductor device with a notched gate electrode A silicon nitride film having a thickness of 3 nm or less is formed on the surfaces of a P-well and N-well, as well as on the upper and side surfaces of a gate electrode, in which the silicon nitride film can be formed, for example, by exposing the surface of the P-... | 07/29/2008 |
| 7361565 | Method of forming a metal gate in a semiconductor device In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is po... | 04/22/2008 |
| 7335567 | Gate electrodes of semiconductor devices and methods of manufacturing the same Gate electrodes of semiconductor devices and methods of manufacturing the same are disclosed. An example method comprises: sequentially forming a gate oxide layer and a sacrificial buffer layer on a semiconductor substrate; patterning the sacrificial buffer layer to... | 02/26/2008 |
| 7306990 | Information storage element, manufacturing method thereof, and memory array An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavi... | 12/11/2007 |
| 7259056 | Method for manufacturing semiconductor device In a method for manufacturing a semiconductor device, gate insulation films and gate electrodes are first formed on a substrate. An impurity is implanted into each gate electrode. Next, a first heat treatment is performed to the substrate for diffusing the impurity ... | 08/21/2007 |
| 7224008 | Self-aligned production method for an insulated gate semiconductor device cell and insulated gate semiconductor device cell The invention relates to a manufacturing method for an insulated gate semiconductor device cell, comprising the steps of forming a cell window (3) in a layered structure that is located on top of a semiconductor substrate (1), forming at least one proc... | 05/29/2007 |
| 7186632 | Method of fabricating a semiconductor device having a decreased concentration of phosphorus impurities in polysilicon In a method for manufacturing a semiconductor device having a laminated gate electrode, a phosphorus-doped polysilicon is formed on a gate oxide film. A high-melting metal or a compound of a high-melting metal and silicon is formed on the polysilicon. Phosphorus is ... | 03/06/2007 |
| 6686604 | Multiple operating voltage vertical replacement-gate (VRG) transistor An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A th... | 02/03/2004 |
| 6664592 | Semiconductor device with groove type channel structure A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom ... | 12/16/2003 |
| 6624065 | Method of fabricating a semiconductor device using a damascene metal gate A method of fabricating a semiconductor device using a damascene metal gate including the steps of forming a damascene gate oxide layer and a damascene gate electrode on a semiconductor substrate, forming a trench at an upper part of the damascene gate el... | 09/23/2003 |
| 6613621 | Methods of forming self-aligned contact pads using a damascene gate process Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the ... | 09/02/2003 |
| 6608356 | Semiconductor device using damascene technique and manufacturing method therefor A gate insulation film is formed on semiconductor substrate, a gate electrodes are formed on the gate insulation film, and source/drain diffusion layers are formed. Silicon nitride films are formed on a side wall of the gate electrodes, a silicon oxide fi... | 08/19/2003 |
| 6589846 | Method for fabricating semiconductor device including self aligned gate An method for fabricating a semiconductor device reduces a size of a MOSFET by self aligning a gate electrode with a device isolation insulation film. Thus, the gate electrode is not overlapped with the device isolation insulation film, differently from a... | 07/08/2003 |
| 6570220 | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition The invention relates to a method of forming reduced feature size spacers. The method includes providing a semiconductor substrate having an area region; patterning a first spacer over a portion of the area region of the substrate, the first spacer having... | 05/27/2003 |
| 6563154 | Polysilicon layer having improved roughness after POCl3 doping An improved method for depositing the polysilicon layer from which a gate pedestal is later formed is described. Deposition takes place in two stages. Initially, the conventional deposition temperature of about 630° C. is used. Then, when the intended th... | 05/13/2003 |
| 6562730 | Barrier in gate stack for improved gate dielectric integrity A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper ... | 05/13/2003 |
| 6548385 | Method for reducing pitch between conductive features, and structure formed using the method A method is described which may be used to reduce a pitch between conductive features. One embodiment of the method involves forming a structure including a substrate, a conductive layer on the substrate, multiple photoresist features arranged on the cond... | 04/15/2003 |
| 6548388 | Semiconductor device including gate electrode having damascene structure and method of fabricating the same A gate electrode conductive layer is formed on an active region that is recessed relative to field oxide layers so as to define a damascene structure. The gate electrode conductive layer is formed on the active region but is not formed on a field region s... | 04/15/2003 |
| 6528403 | Fabrication process of a semiconductor integrated circuit device With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thicknes... | 03/04/2003 |
| 6522007 | Semiconductor device having dummy patterns for metal CMP A gate electrode has a relatively long gate length of e.g., about 10 μm. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending... | 02/18/2003 |
| 6518151 | Dual layer hard mask for eDRAM gate etch process A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and usi... | 02/11/2003 |
| 6518636 | Semiconductor MISFET A conductive film for gate electrode including a polysilicon film is deposited on a semiconductor substrate, and patterned to form gate electrodes. An oxide film is formed on each side face of at least the polysilicon film, and by nitriding at least the s... | 02/11/2003 |
| 6515338 | Semiconductor device and manufacturing method therefor A method of manufacturing semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a firs... | 02/04/2003 |
| 6515348 | Semiconductor device with FET MESA structure and vertical contact electrodes A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of ... | 02/04/2003 |
| 6509609 | Grooved channel schottky MOSFET A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 1017 cm-3. A grooved channel is formed in... | 01/21/2003 |
| 6503819 | Fabrication process of a semiconductor integrated circuit device With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thicknes... | 01/07/2003 |
| 6500718 | Method for fabricating semiconductor device An method for fabricating a semiconductor device reduces a size of a MOSFET by self aligning a gate electrode with a device isolation insulation film. Thus, the gate electrode is not overlapped with the device isolation insulation film, differently from a... | 12/31/2002 |
| 6495897 | Integrated circuit having etch-resistant layer substantially covering shallow trench regions An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching operation performed on the polysilicon layer. The process ... | 12/17/2002 |
| 6436798 | MOSFET device A method of fabricating a MOSFET device with a multiple T-shaped gate has the following steps. A substrate with an active region and a non-active region is provided, wherein the active region has a plurality of trenches, and the non-active region has a pl... | 08/20/2002 |
| 6406950 | Definition of small damascene metal gates using reverse through approach Various methods of fabricating circuit devices incorporating a gate stack are disclosed. In one aspect, a method of fabricating a circuit device on a substrate is provided that includes forming a first insulating film on the substrate and etching the firs... | 06/18/2002 |
| 6392279 | Semiconductor device having LDD structure adapted to lower parasitic capacitance and parasitic resistance The MOS transistor incorporated in a semiconductor device comprises a gate electrode formed on a semiconductor substrate through the medium of a gate insulating film, a first impurity introduced area of an LDD structure composed of a low-concentration imp... | 05/21/2002 |
| 6391697 | Method for the formation of gate electrode of semiconductor device using a difference in polishing selection ratio between polymer and oxide film A method for the formation of a gate electrode with a uniform thickness in the semiconductor device by using a difference in polishing selection ratio between a polymer and an oxide film. The method includes steps of depositing a polymer layer on a semico... | 05/21/2002 |
| 6383872 | Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure.... | 05/07/2002 |
| 6380765 | Double pass transistor logic with vertical gate transistors Systems and methods are provided for double pass transistor logic with vertical gate transistors. The vertical gate transistors have multiple vertical gates which are edge defined such that only a single transistor is required for multiple logic inputs. T... | 04/30/2002 |
| 6373114 | Barrier in gate stack for improved gate dielectric integrity A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper ... | 04/16/2002 |
| 6365943 | High density integrated circuit A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method fo... | 04/02/2002 |
| 6362078 | Dynamic threshold voltage device and methods for fabricating dynamic threshold voltage devices A method of making an active device is provided. A conductive line is formed in a substrate of a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET). The conductive line runs alongside a gate of the MOSFET. The gate is coupled to the conductive lin... | 03/26/2002 |
| 6362074 | Integrated circuit processing with improved gate electrode fabrication An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching operation performed on the polysilicon layer. The process ... | 03/26/2002 |
