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| Number | Title | Issue Date |
| 7435647 | NOR-type flash memory device and manufacturing method thereof A flash memory device that has a structure capable of preventing gate stack damage, and a method of manufacturing the same, is presented. The method includes forming a first photo resist pattern to open a common source region on a substrate where a shallow trench is... | 10/14/2008 |
| 7411245 | Spacer barrier structure to prevent spacer voids and method for forming the same A semiconductor device includes a spacer adjacent a gate structure. A protection layer covers oxide portions of the spacer surface such that subsequent manufacturing operations such as wet oxide etches and strips, do not produce voids in the spacers. A method for fo... | 08/12/2008 |
| 7326607 | Imager floating diffusion region and process for forming same The present invention provides an imager device with a floating diffusion region resistant to charge leakage. The floating diffusion region is formed having a first doped region and a second doped region which has a higher concentration of dopants than the first dop... | 02/05/2008 |
| 6696333 | Method of making integrated circuit with MOSFETs having bi-layer metal gate electrodes A method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes, removing the gate electrodes of the first composition, and repla... | 02/24/2004 |
| 6689654 | Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region an... | 02/10/2004 |
| 6683342 | Memory structure and method for manufacturing the same A memory structure and the method for fabricating the same are disclosed in this present invention. A first gate structure and a second gate structure are provided onto a substrate. After an implanting process, the first gate structure will become the per... | 01/27/2004 |
| 6683352 | Semiconductor device structure A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is dispose... | 01/27/2004 |
| 6674137 | Semiconductor device and its manufacturing method A semiconductor device is disclosed that can include a gate electrode (6) having a lower layer (6a) and a higher layer (6b), a mask insulating film (7) formed over a higher layer (6b). A side surface insulating film (9) may be formed on sides of a gate el... | 01/06/2004 |
| 6670254 | Method of manufacturing semiconductor device with formation of a heavily doped region by implantation through an insulation layer A method of manufacturing semiconductor devices. A gate structure is formed over a substrate. A dopant implantation is carried out to form a lightly doped region in the substrate on each side of the gate structure. An insulation layer is formed over the s... | 12/30/2003 |
| 6667199 | Semiconductor device having a replacement gate type field effect transistor and its manufacturing method The present invention provides a MISFET with a replacement gate electrode, which ensures large ON-current. A semiconductor device, in which on the substrate, first and second field effect transistors are formed, the first field effect transistor is a repl... | 12/23/2003 |
| 6660600 | Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprisi... | 12/09/2003 |
| 6656853 | Enhanced deposition control in fabricating devices in a semiconductor wafer A method for an enhanced deposition control includes forming a transistor on a substrate of a semiconductor wafer, and depositing a silicon nitride layer on the transistor and the substrate in a reactor at a pressure of at least approximately 104 | 12/02/2003 |
| 6649500 | Semiconductor device including an insulated gate field effect transistor and method of manufacturing the same A semiconductor device is disclosed including an IGFET (insulated gate field effect transistor) and a method of manufacturing the same. The semiconductor device may include an oxide film (115) or a nitride film (106) provided on a side surface of a gate e... | 11/18/2003 |
| 6649479 | Method for fabricating MOSFET device A MOSFET device includes a gate formed on a multi-surface area of a semiconductor substrate formed of a first surface which is not etched, a second surface etched in parallel with the first surface, and a surface connecting the first and second surfaces. ... | 11/18/2003 |
| 6646326 | Method and system for providing source/drain-gate spatial overlap engineering for low-power devices A method and system for providing a semiconductor device on a substrate are disclosed. The method and system include providing a tunneling barrier on the substrate and providing at least one gate on the tunneling barrier. The at least one of gate includes... | 11/11/2003 |
| 6645806 | Methods of forming DRAMS, methods of forming access transistors for DRAM devices, and methods of forming transistor source/drain regions The invention includes a DRAM device. The device has an access transistor construction, and the access transistor construction has a pair of source/drain regions. A halo region is associated with one of the source/drain regions of the access transistor co... | 11/11/2003 |
| 6642114 | Semiconductor device and method for fabricating the same A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insula... | 11/04/2003 |
| 6638805 | Method of fabricating a DRAM semiconductor device A method of fabricating a DRAM semiconductor device including forming gate stacks in which a gate pattern and a gate sacrificial mask are sequentially deposited on a semiconductor substrate, forming an etch stopper on the semiconductor substrate, forming ... | 10/28/2003 |
| 6635943 | Method and system for reducing charge gain and charge loss in interlayer dielectric formation A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capa... | 10/21/2003 |
| 6635538 | Method of manufacturing a semiconductor device When sidewalls (10) are formed by anisotropic etching, an insulating film (9) serves as a protective film for a major surface of a semiconductor substrate (100) and therefore prevents the major surface from suffering etching damage. That relieves an elect... | 10/21/2003 |
| 6624065 | Method of fabricating a semiconductor device using a damascene metal gate A method of fabricating a semiconductor device using a damascene metal gate including the steps of forming a damascene gate oxide layer and a damascene gate electrode on a semiconductor substrate, forming a trench at an upper part of the damascene gate el... | 09/23/2003 |
| 6617259 | Method for fabricating semiconductor device and forming interlayer dielectric film using high-density plasma A method for fabricating a semiconductor device and forming an insulating film used therein, includes forming an isolation insulating film on a semiconductor wafer and forming gates, separated by gaps having a predetermined distance, on an active region. ... | 09/09/2003 |
| 6613616 | Method for fabricating field-effect transistors in integrated semiconductor circuits and integrated semiconductor circuit fabricated with a field-effect transistor of this type including a dual gate A method for fabricating a field-effect transistor situated within an integrated semiconductor circuit. At least two gate regions each extending between a source region and a drain region and are disposed such that they lie one above the other in a thickn... | 09/02/2003 |
| 6614079 | All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS A complementary metal oxide semiconductor (CMOS) device having silicide contacts that are self-aligned to deep junction edges formed within a surface of a semiconductor substrate as well as a method of manufacturing the same are disclosed. Specifically, t... | 09/02/2003 |
| 6613624 | Method for fabricating an integrated semiconductor circuit Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel region by an altered work function of the electrons. Transistors in semiconductor circuits havin... | 09/02/2003 |
| 6608356 | Semiconductor device using damascene technique and manufacturing method therefor A gate insulation film is formed on semiconductor substrate, a gate electrodes are formed on the gate insulation film, and source/drain diffusion layers are formed. Silicon nitride films are formed on a side wall of the gate electrodes, a silicon oxide fi... | 08/19/2003 |
| 6599792 | Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same, wherein a gate electrode structure is formed on a surface of a semiconductor substrate. Next, a gate poly oxide (GPOX) layer is deposited on a surface of the gate electrode structure and on t... | 07/29/2003 |
| 6586289 | Anti-spacer structure for improved gate activation A method and structure for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a structure having a plurality of patterned g... | 07/01/2003 |
| 6579751 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type... | 06/17/2003 |
| 6569743 | Method of fabricating a semiconductor device A method of fabricating a semiconductor device is provided. In this method, a gate insulating layer and a gate are sequentially formed on a semiconductor substrate of a first conductivity type. A first active region of a second conductivity type is formed... | 05/27/2003 |
| 6563183 | Gate array with multiple dielectric properties and method for forming same The invention provides an integrated circuit fabricated on a semiconductor substrate. The integrated circuit comprises a first field effect transistor and a second field effect transistor. The first field effect transistor comprises a first polysilicon ga... | 05/13/2003 |
| 6555450 | Contact forming method for semiconductor device A contact forming method of a semiconductor device is disclosed, in which a pad polysilicon layer is formed at an active region of a cell array, thereafter an upper portion of a gate is opened when a spacer of a NMOS transistor region is formed. And at th... | 04/29/2003 |
| 6555868 | Semiconductor device and method of manufacturing the same A major object is to provide an improved semiconductor device capable of preventing occurrence of a crystal defect in a substrate. A source region is arranged at a surface of a semiconductor substrate and between first and second layered gates. A sidewall spac... | 04/29/2003 |
| 6548862 | Structure of semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low para... | 04/15/2003 |
| 6548359 | Asymmetrical devices for short gate length performance with disposable sidewall An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of th... | 04/15/2003 |
| 6548845 | Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate, a gate electrode formed over the semiconductor substrate and a first interlevel insulating layer which is formed over the semiconductor substrate and has first and second contact holes defined by ... | 04/15/2003 |
| 6544849 | Method of fabricating semiconductor device for preventing polysilicon line being damaged during removal of photoresist A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection dev... | 04/08/2003 |
| 6531736 | Semiconductor device and method of manufacturing thereof In the manufacture of a semiconductor device having a logic section and a memory section built in the same chip, a thin layer of refractory metal (titanium: Ti) is deposited by sputtering in the logic section with the entire memory section covered with a ... | 03/11/2003 |
| 6512299 | Semiconductor device and a manufacturing process therefor This invention provides a semiconductor device comprising gate insulating films 13, 21 formed on the main surface of a silicon substrate 11; gate electrodes 14, 22 consisting of polycrystalline silicon; and a high-density doped layer 17, wherein a part of... | 01/28/2003 |
| 6503795 | Method for fabricating a semiconductor device having a storage cell The present invention discloses a method for fabricating a semiconductor device. In an open bit line cell aligned local interconnection type device having a minimum line width of 1F and a pattern interval of 1F, hard masks are formed on respective conduct... | 01/07/2003 |
