Class 257/E21.619 - With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.616. This subclass
No. of patents: 154
Last issue date: 09/30/2008

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Number	Title	Issue Date
7429512	Method for fabricating flash memory device A method of fabricating a flash memory device. A DDD ion is implanted into a high voltage PMOS transistor and into source and drain junctions of a cell transistor in order to facilitate a pinch-off phenomenon in the gate to drain overlap region and also increase the...	09/30/2008
7423323	Semiconductor device with raised segment A device having a raised segment, and a manufacturing method for same. An SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the insulating layer. The semiconductor material ...	09/09/2008
7414277	Memory cell having combination raised source and drain and method of fabricating same A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, w...	08/19/2008
7410875	Semiconductor structure and fabrication thereof A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in...	08/12/2008
7393766	Process for integration of a high dielectric constant gate insulator layer in a CMOS device A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polys...	07/01/2008
7390711	MOS transistor and manufacturing method thereof A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended sourc...	06/24/2008
7348232	Highly activated carbon selective epitaxial process for CMOS In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a drain region by doping a first portion and a second portion of active regions adjacent the gate, and formin...	03/25/2008
7348233	Methods for fabricating a CMOS device including silicide contacts Methods are provided for fabricating a CMOS device having a silicon substrate including a first N-type region and a second P-type region. The method includes the steps of forming a first gate electrode overlying the first N-type region and a second gate electrode ov...	03/25/2008
7335566	Polysilicon gate doping method and structure for strained silicon MOS transistors A method of fabricating an integrated circuit including strained silicon bearing regions. The method forms a blanket layer of material having an initial thickness overlying a source region, a drain region, and a gate structure of an MOS device to cover an upper surf...	02/26/2008
7306997	Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spa...	12/11/2007
7300846	Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are disclosed, in which an insulating layer may be formed in a strained silicon layer under source/drain regions to substantially overcome conventional problems resulting from a channel decrease in the s...	11/27/2007
7279389	Technique for forming a transistor having raised drain and source regions with a tri-layer hard mask for gate patterning By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be acc...	10/09/2007
7268048	Methods for elimination of arsenic based defects in semiconductor devices with isolation regions Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a ...	09/11/2007
7259056	Method for manufacturing semiconductor device In a method for manufacturing a semiconductor device, gate insulation films and gate electrodes are first formed on a substrate. An impurity is implanted into each gate electrode. Next, a first heat treatment is performed to the substrate for diffusing the impurity ...	08/21/2007
7202132	Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area. ...	04/10/2007
7118977	System and method for improved dopant profiles in CMOS transistors According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a gate stack on an outer surface of a semiconductor body. First and second sidewall bodies are formed on opposing sides of the gate stack. A first reces...	10/10/2006
7119369	FET having epitaxial silicon growth A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline ma...	10/10/2006
7074683	Semiconductor devices and methods of fabricating the same A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may...	07/11/2006
6686059	Semiconductor device manufacturing method and semiconductor device A semiconductor device having a reduced overlap capacity between a gate electrode and extensions. Specifically, a stacked structure made up of a polysilicon film, tungsten silicide film, and silicon nitride film is partially formed in first and second reg...	02/03/2004
6670245	Method for fabricating an ESD device The present invention provides a method for fabricating an ESD device. First, a substrate undergoes first implantation to form a first first-type well comprising an electrostatic discharge region. Next, second implantation is performed on the substrate an...	12/30/2003
6670227	Method for fabricating devices in core and periphery semiconductor regions using dual spacers For fabricating a first device within a core region and a second device within a periphery region, of a semiconductor substrate, disposable spacers having a first width are formed at sidewalls of a first gate stack of the core region and a second gate sta...	12/30/2003
6660595	Implantation method for simultaneously implanting in one region and blocking the implant in another region A method of fabricating different transistor structures with the same mask. A masking layer (214) has two openings (204, 202) that expose two transistor areas (304,302). The width of the second opening (202) is adjusted such that the angled implant is sub...	12/09/2003
6649481	Methods of fabricating a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned mann...	11/18/2003
6646295	Semiconductor device A semiconductor device including an insulated gate field effect transistor (IGFET) has been disclosed. The IGFET may be formed in an element region defined by an element isolation region (14) formed on a semiconductor substrate (8). A covering portion (10...	11/11/2003
6642589	Semiconductor device having pocket and manufacture thereof A semiconductor device has first and second active regions defined on the principal surface of a silicon substrate, a first n-channel MOS transistor formed in the first active region and having first extension regions and first pocket regions being deeper...	11/04/2003
6635938	Semiconductor device and manufacturing method thereof A polysilicon nitride film is formed to cover a polysilicon gate. By heat treatment of the silicon nitride film in an oxygen atmosphere, a silicon oxinitride film is formed. By anisotropically etching the silicon oxinitride film and the silicon nitride fi...	10/21/2003
6633059	Semiconductor device having MOS transistor A p type well region, a field insulation film, a gate insulation film, and a gate-use poly-Si layer are formed on the surface of a silicon substrate, after which a laminate of a silicon nitride layer and a resist layer is used as a mask in ion implantatio...	10/14/2003
6627963	Method for fabricating a merged integrated circuit device The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the ...	09/30/2003
6621146	Method and apparatus for the use of embedded resistance to linearize and improve the matching properties of transistors An integrated circuit includes a substrate and a degenerated transistor. The degenerated transistor includes a control terminal formed on the substrate, a channel formed in the substrate beneath the first control terminal, first and second heavily-doped r...	09/16/2003
6617214	Integrated circuit structure and method therefore An integrated circuit is made with transistors having varying characteristics in the same well. One transistor, which is particularly useful as an I/O device, has a relatively deep source/drain with a relatively thick gate dielectric. The well doping is s...	09/09/2003
6607964	Method of manufacturing semiconductor device A first silicide protection film is deposited on a silicon substrate, a first resist pattern having an opening at a prescribed position is formed, a portion of the first silicide protection film exposed from the opening of the first resist pattern is remo...	08/19/2003
6599795	Method of manufacturing semiconductor device including a step of forming a silicide layer, and semiconductor device manufactured thereby A gate insulating film 2 is formed on a DRAM circuit region 11 and a logic circuit region 12 of a semiconductor substrate, and gate electrodes 3 are formed on the gate insulating film 2. Sidewalls of the gate electrodes 3 are oxidized. A first insulating ...	07/29/2003
6596593	Method of manufacturing semiconductor device employing oxygen implantation Disclosed is a semiconductor device having a reduced size, increased accuracy, and flattened element isolation regions with an decreased size. A plurality of MOSFETs having gate oxide films with different thicknesses and element isolation regions are form...	07/22/2003
6573583	Semiconductor device and method of manufacturing the same Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a...	06/03/2003
6544872	Dopant implantation processing for improved source/drain interface with metal silicides Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices is avoided, or at least substantially reduced, b...	04/08/2003
6515348	Semiconductor device with FET MESA structure and vertical contact electrodes A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of ...	02/04/2003
6512296	Semiconductor structure having heterogenous silicide regions having titanium and molybdenum A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited ...	01/28/2003
6509243	Method for integrating high-voltage device and low-voltage device In a method for integrating a high-voltage device and a low-voltage device, a substrate includes a first isolation region separating a high-voltage device region and a low-voltage device region, a second isolation region formed in a scribe region, and a p...	01/21/2003
6495882	Short-channel schottky-barrier MOSFET device A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket impl...	12/17/2002
6489223	Angled implant process Different symmetrical and asymmetrical devices are formed on the same chip using non-critical block masks and angled implants. A barrier is selectively formed adjacent one side of a structure and this barrier blocks dopant implanted at an angle toward the...	12/03/2002

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Class 257/E21.619 - With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)