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| Number | Title | Issue Date |
| 7405128 | Dotted channel MOSFET and method A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) ... | 07/29/2008 |
| 7402497 | Transistor device having an increased threshold stability without drive current degradation By removing a portion of a halo region or by avoiding the formation of the halo region within the extension region, which may be subsequently formed on the basis of a re-grown semiconductor material, the threshold roll off behavior may be significantly improved, whe... | 07/22/2008 |
| 7393767 | Method for implanting a cell channel ion of semiconductor device A method for implanting a cell channel ion of semiconductor device is disclosed. In accordance with the method, the bit line contact region and the edge portion of the channel region adjacent to the bit line contact region in the cell region are subjected to a selec... | 07/01/2008 |
| 7378321 | Method for patterning a semiconductor component In a method for patterning a semiconductor component a first cover layer is applied to a first region and a second region of a semiconductor component being arranged in a semiconductor substrate. The first region is different from the second region. The first cover ... | 05/27/2008 |
| 7348243 | Semiconductor device and method for fabricating the same A transistor and a method for fabricating the same is disclosed, to uniformly provide impurity ions in impurity areas, and to prevent a short channel effect, in which the method for fabricating the transistor includes steps of forming a plurality of channel ion impl... | 03/25/2008 |
| 7329618 | Ion implanting methods An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally pulled away from one another with a patterned photoresist layer received ... | 02/12/2008 |
| 7326972 | Interconnect structure in integrated circuits A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths. ... | 02/05/2008 |
| 7312136 | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free ... | 12/25/2007 |
| 7300845 | Method of manufacturing recess type MOS transistor having a dual diode impurity layer structure The method of manufacturing a recess type MOS transistor improves a refresh characteristic. In the method, a channel impurity region is formed by ion implanting a first conductive impurity in an active region of a semiconductor substrate. Thereon, a second conductiv... | 11/27/2007 |
| 7282414 | Fabrication methods for compressive strained-silicon and transistors using the same Fabrication methods for compressive strained-silicon by ion implantation. Ions are implanted into a silicon-containing substrate and high temperature processing converts the vicinity of the ion-contained region into strained-silicon. Transistors fabricated by the me... | 10/16/2007 |
| 7279388 | Method for manufacturing transistor in semiconductor device Disclosed is a method for manufacturing a transistor in a semiconductor device, which can improve a device's refresh characteristics. The method includes: providing a silicon substrate having active and field regions; performing a channel ion implantation into the s... | 10/09/2007 |
| 7253060 | Gate-all-around type of semiconductor device and method of fabricating the same A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mo... | 08/07/2007 |
| 7176095 | Bi-modal halo implantation Methods of fabricating halo regions are provided. In one aspect, a method is provided of fabricating a first halo region and a second halo region for a circuit device of a first conductivity type and having a gate structure with first and second sidewalls. The first... | 02/13/2007 |
| 7144782 | Simplified masking for asymmetric halo Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor gate and an asymmetric transistor gate on a substrate. The symmetric and asymmetric transistor gates are subs... | 12/05/2006 |
| 6855984 | Process to reduce gate edge drain leakage in semiconductor devices The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted n-type dopants counteract portions of strongly p-type HALO or pocket regions creating a smoother dopant profil... | 02/15/2005 |
| 6703688 | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... | 03/09/2004 |
| 6683345 | Semiconductor device and method for making the device having an electrically modulated conduction channel A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaini... | 01/27/2004 |
| 6680226 | Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the dra... | 01/20/2004 |
| 6677192 | Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... | 01/13/2004 |
| 6653686 | Structure and method of controlling short-channel effect of very short channel MOSFET A semiconductor device comprising a gate having an approximately 0.05 μm channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the ... | 11/25/2003 |
| 6646322 | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... | 11/11/2003 |
| 6642589 | Semiconductor device having pocket and manufacture thereof A semiconductor device has first and second active regions defined on the principal surface of a silicon substrate, a first n-channel MOS transistor formed in the first active region and having first extension regions and first pocket regions being deeper... | 11/04/2003 |
| 6638832 | Elimination of narrow device width effects in complementary metal oxide semiconductor (CMOS) devices Neutral conductivity ions, preferably germanium, are implanted through the oxide of a metal oxide semiconductor after isolation formation to provide a nearly constant threshold voltage for transistor operation independent of transistor channel width as de... | 10/28/2003 |
| 6627963 | Method for fabricating a merged integrated circuit device The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the ... | 09/30/2003 |
| 6613659 | Manufacturing method of gate insulating film of multiple thickness A semiconductor device having a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over th... | 09/02/2003 |
| 6608355 | Semiconductor integrated circuit having anti-fuse, method of fabricating, and method of writing data in the same A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of... | 08/19/2003 |
| 6600195 | Semiconductor device A semiconductor device capable of preventing variations in threshold voltage and having high reliability is provided. The semiconductor device includes a semiconductor substrate having a semiconductor region, and a field-effect transistor. The field-effec... | 07/29/2003 |
| 6597026 | Semiconductor device comprising plural isolated channels in a shallow trench isolation region A semiconductor device includes a plurality of shallow trench isolation bands, a plurality of channels, a source electrode, a drain electrode, and a gate electrode. The shallow trench isolation bands are formed in a band-like shape within an element forma... | 07/22/2003 |
| 6593191 | Buried channel strained silicon FET using a supply layer created through ion implantation A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supp... | 07/15/2003 |
| 6593641 | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... | 07/15/2003 |
| 6583467 | Semiconductor integrated circuit device In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes... | 06/24/2003 |
| 6583066 | Methods for fabricating a semiconductor chip having CMOS devices and fieldless array A method for etching an oxide-nitride-oxide (ONO) layer fabricated on a semiconductor wafer, the ONO layer including a lower oxide layer, a nitride layer located over the lower oxide layer, and an upper oxide layer located over the nitride layer. The meth... | 06/24/2003 |
| 6580154 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility ... | 06/17/2003 |
| 6579751 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type... | 06/17/2003 |
| 6555839 | Buried channel strained silicon FET using a supply layer created through ion implantation A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or burie... | 04/29/2003 |
| 6548862 | Structure of semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low para... | 04/15/2003 |
| 6528847 | Metal oxide semiconductor device having contoured channel region and elevated source and drain regions A metal oxide semiconductor (MOS) device includes a silicon substrate, source and drain regions having a predetermined junction depth (dj) relative to the surface of the silicon substrate, and a gate region having a contoured channel region for... | 03/04/2003 |
| 6509220 | Method of fabricating a high-voltage transistor A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to f... | 01/21/2003 |
| 6495882 | Short-channel schottky-barrier MOSFET device A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket impl... | 12/17/2002 |
| 6489223 | Angled implant process Different symmetrical and asymmetrical devices are formed on the same chip using non-critical block masks and angled implants. A barrier is selectively formed adjacent one side of a structure and this barrier blocks dopant implanted at an angle toward the... | 12/03/2002 |
