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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Number | Title | Issue Date |
| 7429503 | Method of manufacturing well pick-up structure of non-volatile memory A method of manufacturing a well pick-up structure of a non-volatile memory is provided. A substrate including a first conductive type well, device isolation structures and dummy memory columns is provided. Each of the dummy memory columns includes a second conducti... | 09/30/2008 |
| 6642599 | Semiconductor device and method of manufacturing the same A high resistance n-type base layer is formed on a silicon substrate with an insulating layer made of a silicon oxide film therebetween. In the high resistance n-type base layer a p-ch MOS transistor is formed. The p-ch MOS transistor is electrically isol... | 11/04/2003 |
| 6638776 | Thermal characterization compensation A method of standardizing a fabrication process for an integrated circuit. The fabrication process includes a preceding thermal energy sensitive process and at least one set of selectable succeeding thermal energy delivery processes. An integrated circuit... | 10/28/2003 |
| 6611680 | Radio architecture A digital radio transceiver integrated circuit includes MOS transistors with normal threshold voltages in the digital circuits, and with reduced threshold voltages in at least some of the analog RF components. This allows the transceiver to be reduced in ... | 08/26/2003 |
| 6586311 | Salicide block for silicon-on-insulator (SOI) applications A method is provided, the method comprising forming a buffer layer above a structure layer, and forming a dielectric layer above the buffer layer. The method also comprises patterning the dielectric layer to form a salicide block above a portion of the st... | 07/01/2003 |
| 6545327 | Semiconductor device having different gate insulating films with different amount of carbon A manufacturing method produces a semiconductor IC device which can maintain a low power consumption for electronic circuits and form gate-isolation layers of different thicknesses without increasing the manufacturing cost. The semiconductor IC device has... | 04/08/2003 |
| 6501147 | Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtained A process for manufacturing an electronic device having an HV MOS transistor with a low multiplication coefficient and a high threshold in a non-implanted area of the substrate, this area having the same conductivity type and the same doping level as the ... | 12/31/2002 |
| 6483152 | Semiconductor device A semiconductor device and a method of fabricating the same are disclosed. A resistor, a lower plate of an analog capacitor and a gate electrode of a MOS transistor are simultaneously formed over a substrate where an isolation film is formed. Junction reg... | 11/19/2002 |
| 6461070 | Document folder and method A document folder has a cover formed of relatively flexible sheet material with a back and front panels, and a spine hingedly connecting the panels so that they may be disposed in an overlying position and provide an enclosure for documents therebetween. ... | 10/08/2002 |
| 6448125 | Electronic power device integrated on a semiconductor material and related manufacturing process An electronic power device is integrated on a substrate of semiconductor material having a first conductivity type, on which an epitaxial layer of the same type of conductivity is grown. The power device comprises a power stage PT and a control stage CT, ... | 09/10/2002 |
| 6441444 | Semiconductor device having a nitride barrier for preventing formation of structural defects Providing a method of producing a semiconductor device and a structure of the semiconductor device employing a trench isolation structure for isolating semiconductor elements wherein volumetric expansion of a trench-filling material due to oxidation proce... | 08/27/2002 |
| 6399986 | Semiconductor device and method of fabricating the same The present invention relates to a semiconductor device and a method of fabricating the same. A semiconductor device having first and second transistor regions and a field region includes a semiconductor substrate having a first type conductivity, a first... | 06/04/2002 |
| 6344416 | Deliberate semiconductor film variation to compensate for radial processing differences, determine optimal device characteristics, or produce small productions Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production r... | 02/05/2002 |
| 6342440 | Method for forming low-leakage impurity regions by sequence of high-and low-temperature treatments A method of manufacturing a semiconductor device capable of suppressing increase of a leakage current resulting from a high-temperature heat treatment is obtained. In this manufacturing method, an impurity region is formed by selectively ion-implanting an... | 01/29/2002 |
| 6309937 | Method of making shallow junction semiconductor devices Disclosed is a technique to provide an integrated circuit substrate with a transistor gate member that has opposing sidewalls. A first spacer extends from one of the sidewalls and a second spacer extends from another of the sidewalls. A source region and ... | 10/30/2001 |
| 6271566 | Semiconductor device having a carbon containing insulation layer formed under the source/drain A manufacturing method produces a semiconductor IC device which can maintain a low power consumption for electronic circuits and form gate-isolation layers of different thicknesses without increasing the manufacturing cost. The semiconductor IC device has... | 08/07/2001 |
| 6271572 | Multi-voltage level semiconductor device and its manufacture In a semiconductor device comprising a MOS transistor driven at a relatively low voltage and a MOS transistor driven at a relatively high voltage formed on the same semiconductor substrate, the MOS transistor driven at the relatively high voltage comprise... | 08/07/2001 |
| 6268249 | Semiconductor device and method of fabricating the same The present invention relates to a semiconductor device and a method of fabricating the same. A semiconductor device having first and second transistor regions and a field region includes a semiconductor substrate having a first type conductivity, a first... | 07/31/2001 |
| 6258701 | Process for forming insulating structures for integrated circuits A process for forming insulating structures for integrated circuits that includes depositing a silicon oxide layer; shaping the silicon oxide layer to form first delimiting walls of the insulating regions substantially perpendicular to the substrate; and ... | 07/10/2001 |
| 6245610 | Method of protecting a well at a floating stage A method of protecting a well at a floating stage. In a first conductive type substrate, a second conductive type well is formed. A first conductive type heavily doped region and a second conductive type heavily doped region are respectively formed in the... | 06/12/2001 |
| 6242295 | Method of fabricating a shallow doped region for a shallow junction transistor A method of forming a plurality of shallow junction transistors, the method comprising the steps of providing a substrate (10) having a first region (13) and a second region (15). The first region (13) and the second region (15) include a first channel re... | 06/05/2001 |
| 6235590 | Fabrication of differential gate oxide thicknesses on a single integrated circuit chip Techniques for fabricating integrated circuits having devices with gate oxides having different thicknesses and a high nitrogen content include forming the gate oxides at pressures at least as high as 2.0 atmospheres in an ambient of a nitrogen-containing... | 05/22/2001 |
| 6232244 | Methodology for achieving dual gate oxide thicknesses Dual gate oxide layer thicknesses are achieved by depositing a thin blocking layer on active regions of a semiconductor substrate, such as silicon nitride, oxynitride, or oxide. Selected active regions are nitridated through a patterned photoresist mask f... | 05/15/2001 |
| 6221723 | Method of setting threshold voltage levels of a multiple-valued mask programmable read only memory A method of setting a plurality of different threshold voltage levels to a plurality of cell regions for a mask programmable semiconductor device by carrying out a second impurity first-code selective ion-implantation, into at least a first-selected one o... | 04/24/2001 |
| 6190987 | MOS semiconductor device and method of manufacturing the same A semiconductor device includes a first diffusion layer, an insulating film, and an electrode. The first diffusion layer is formed on the surface of a first-conductivity-type semiconductor substrate and has an opposite conductivity type. The insulating fi... | 02/20/2001 |
| 6166404 | Semiconductor device in which at least two field effect transistors having different threshold voltages are formed on a common base A semiconductor device including field effect transistors having different threshold voltages formed on a common base, characterized by including: a first field effect transistor having a p-n junction gate; and a second field effect transistor having a Sc... | 12/26/2000 |
| 6153453 | JFET transistor manufacturing method The present invention relates to a method of manufacturing a JFET transistor in an integrated circuit containing complementary MOS transistors, this JFET transistor being formed in an N-type well of a P-type substrate, including the steps of forming a P-t... | 11/28/2000 |
| 6133115 | Formation of gate electrode The invention relates to an improvement in formation of a gate electrode. In the invention, there are formed first and second oxides on a surface of a substrate. The second oxides have a top surface higher by a height H than top surfaces of the first oxid... | 10/17/2000 |
| 6097047 | Ferroelectric semiconductor device, and ferroelectric semiconductor substrate A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwich... | 08/01/2000 |
| 6080682 | Methodology for achieving dual gate oxide thicknesses Dual gate oxide layer thicknesses are achieved by depositing a thin blocking layer on active regions of a semiconductor substrate, such as silicon nitride, oxynitride, or oxide. Selected active regions are nitridated through a patterned photoresist mask f... | 06/27/2000 |
| 6078078 | V-gate transistor An integrated circuit and a method of making a transistor thereof are provided. The integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas. Each of the transistors has a gate dielectric layer with ... | 06/20/2000 |
| 6074938 | Method of forming a semiconductor device comprising a dummy polysilicon gate electrode short-circuited to a dummy element region in a substrate The present invention relates to a semiconductor device wherein a dummy gate electrode is fixed to the same electric potential as that of a substrate, the stable operation of an LSI is maintained and the process margin is large, and also to a producing me... | 06/13/2000 |
| 6069036 | Method of fabricating semiconductor device A semiconductor device and a method of fabricating the same are disclosed. A resistor, a lower plate of an analog capacitor and a gate electrode of a MOS transistor are simultaneously formed over a substrate where an isolation film is formed. Junction reg... | 05/30/2000 |
| 6057194 | Method of forming trench transistor in combination with trench array An IGFET in combination with a trench array is disclosed. A semiconductor substrate includes first and second x-direction trenches and first, second and third y-direction trenches generally orthogonal to intersecting with the x-direction trenches. The x-d... | 05/02/2000 |
| 6054374 | Method of scaling dielectric thickness in a semiconductor process with ion implantation A semiconductor fabrication process including a method of controlling the gate dielectric film thickness without adjusting the oxidation recipe. A sacrificial dielectric layer is formed on an upper surface of a semiconductor substrate. An oxidation inhibi... | 04/25/2000 |
| 6051509 | Semiconductor integrated circuit manufacturing method and device A manufacturing method produces a semiconductor IC device which can maintain a low power consumption for electronic circuits and form gate-isolation layers of different thicknesses without increasing the manufacturing cost. The semiconductor IC device has... | 04/18/2000 |
| 6027965 | Method of manufacturing an integrated circuit with MOS transistors having high breakdown voltages, and with precision resistors The method described provides for the formation of an implantation mask of polycrystalline silicon comprising strips for providing the gate electrodes of the MOS transistors and portions defining openings for the formation of resistors. The method further... | 02/22/2000 |
| 5998828 | Semiconductor device having nitrogen introduced in its polysilicon gate In a semiconductor device and a method of manufacturing the same according to the present invention, a trade-off relationship between threshold values and a diffusion layer leakage is eliminated and it is not necessary to form gate oxide films at more tha... | 12/07/1999 |
| 5960286 | Method of manufacturing power semiconductor devices A method of manufacturing power semiconductor device, having an area of 3 cm2 or more, comprises the step of preparing a power semiconductor device divided into cell blocks and forming power semiconductor elements whose minimum linewidth is les... | 09/28/1999 |
| 5950082 | Transistor formation for multilevel transistors A dual level transistor and a fabrication technique for making the transistor. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an uppe... | 09/07/1999 |
