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| Number | Title | Issue Date |
| 7439594 | Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich s... | 10/21/2008 |
| 7410884 | 3D integrated circuits using thick metal for backside connections and offset bumps Backside connections for 3D integrated circuits and methods to fabricate thereof are described. A stack of a first wafer over a second wafer that has a substrate of the first wafer on top of the stack, is formed. The substrate of the first wafer is thinned. A first ... | 08/12/2008 |
| 7375420 | Large area transducer array A large area transducer array comprising a substrate having a front side and a backside, a plurality of transducers disposed on the front side of the substrate and patterned in the form of a two-dimensional transducer array in the X-Y plane, a plurality of connector... | 05/20/2008 |
| 7375419 | Stacked mass storage flash memory package A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and sub... | 05/20/2008 |
| 7368337 | Semiconductor device and manufacturing method thereof A semiconductor device and method of manufacturing the same are disclosed. An example semiconductor device includes a semiconductor substrate having a first well, a first source electrode, a drain electrode, and a first gate insulation layer formed on the semiconduc... | 05/06/2008 |
| 7355273 | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. Th... | 04/08/2008 |
| 7354809 | Method for double-sided processing of thin film transistors This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods a... | 04/08/2008 |
| 7355271 | Flexible assembly of stacked chips A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( | 04/08/2008 |
| 7345370 | Wiring patterns formed by selective metal plating Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The ... | 03/18/2008 |
| 7335558 | Method of manufacturing NAND flash memory device A method of manufacturing a NAND flash memory device, including the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined; simultaneously forming a plurality of cell gates on the semiconductor substrate of the... | 02/26/2008 |
| 7335974 | Multi stack packaging chip and method of manufacturing the same A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; ... | 02/26/2008 |
| 7312487 | Three dimensional integrated circuit A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel an... | 12/25/2007 |
| 7304375 | Castellation wafer level packaging of integrated circuit chips Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and i... | 12/04/2007 |
| 7298038 | Integrated circuit package system including die stacking An integrated circuit package system including a leadframe having an aperture provided therein and an integrated circuit package mounted to the leadframe over or under the aperture. A die is mounted within the aperture to the integrated circuit package and the die i... | 11/20/2007 |
| 7298037 | Stacked integrated circuit package-in-package system with recessed spacer A stacked integrated circuit package-in-package system is provided forming a first integrated circuit spacer package including a mold compound with a recess provided therein, stacking the first integrated circuit spacer package on an integrated circuit die on a subs... | 11/20/2007 |
| 7262506 | Stacked mass storage flash memory package A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and sub... | 08/28/2007 |
| 7247933 | Thin multiple semiconductor die package A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (1... | 07/24/2007 |
| 7211472 | Method for producing a multichip module and multichip module A method for producing a multi-chip module having application of at least one contact elevation onto a substrate, application and patterning of a rewiring device onto the substrate and the at least one contact elevation with provision of a contact device on the at l... | 05/01/2007 |
| 7211488 | Method of forming inter-dielectric layer in semiconductor device The present invention relates to a method of forming an interlayer dielectric film in a semiconductor device. More particularly, the present invention selectively forms an insulating film spacer only at a region where a plug is formed between metal lines and removes... | 05/01/2007 |
| 7157787 | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, ... | 01/02/2007 |
| 7126212 | Three dimensional device integration method and integrated device A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after b... | 10/24/2006 |
| 6690026 | Method of fabricating a three-dimensional array of active media An apparatus comprising control circuitry formed on a substrate, and a plurality of active media coupled to the control circuitry and formed in a plurality of planes over the substrate. A method comprising forming a pair of junction regions on a substrate... | 02/10/2004 |
| 6687147 | Cubic memory array with diagonal select lines A method of creating a memory circuit preferably includes (1) forming a first plurality of select-lines in a plane substantially parallel to a substrate, (2) forming a second plurality of select-lines in a plane substantially parallel to the substrate, wh... | 02/03/2004 |
| 6670209 | Embedded metal scheme for liquid crystal display (LCD) application A process for forming a planarized metal layer by forming the plug and overlying metal interconnect simultaneously in order to maintain a uniform gap between the passivation layer of a bottom substrate and the top substrate of a LCD integrated circuit dev... | 12/30/2003 |
| 6667196 | Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method High quality epitaxial layers of monocrystalline oxide materials (24) are grown overlying monocrystalline substrates such as large silicon wafers (22) using RHEED information to monitor the growth rate of the growing film. The monocrystalline oxide layer ... | 12/23/2003 |
| 6657229 | Semiconductor device having multiple transistors sharing a common gate A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, which may be of oppo... | 12/02/2003 |
| 6653677 | Semiconductor constructions The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper su... | 11/25/2003 |
| 6649505 | Method for fabricating and identifying integrated circuits and self-identifying integrated circuits Two types of topologically different three-dimensional integrated circuits (for example a 4-layer three-dimensional memory array and an 8-layer three-dimensional memory array) are fabricated from a single set of photolithographic masks. In one example, ma... | 11/18/2003 |
| 6638800 | Laser processing apparatus and laser processing process A laser processing process which comprises laser annealing a silicon film 2 μm or less in thickness by irradiating at laser beam 400 nm or less in wavelength and being operated in pulsed mode with a pulse width of 50 nsec or more, and preferably, 100 nse... | 10/28/2003 |
| 6638834 | Methods of forming semiconductor constructions The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper su... | 10/28/2003 |
| 6635552 | Methods of forming semiconductor constructions The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper su... | 10/21/2003 |
| 6636185 | Head-mounted display system A head mounted display system including a high resolution active matrix display which reduces center of gravity offset in a compact design. The active matrix display can be either a liquid crystal display or a light emitting display.... | 10/21/2003 |
| 6627530 | Patterning three dimensional structures The invention is directed to a method of forming a three dimensional circuit including introducing a three dimensional circuit over a substrate. In one embodiment, the three dimensional circuit includes a circuit structure in a stacked configuration betwe... | 09/30/2003 |
| 6627953 | High density electronic circuit modules The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of comp... | 09/30/2003 |
| 6617702 | Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the... | 09/09/2003 |
| 6593978 | Method for manufacturing active matrix liquid crystal displays The invention relates to the formation of arrays of thin film transistors (TFT's) on silicon substrates and the dicing and tiling of such substrates for transfer to a common module body. TFT's activate display electrodes formed adjacent the transistors af... | 07/15/2003 |
| 6583030 | Method for producing an integrated circuit processed on both sides A method for producing an integrated circuit wherein a substrate is provided that includes a circuit structure and a first metalization structure disposed thereover comprising at least one layer with plated holes extending therethrough and into the circui... | 06/24/2003 |
| 6570221 | Bonding of silicon wafers The invention concerns the use of spin-on-glass (SOG) to bond two layers of semiconductor together, in order to form a Silicon-on-Insulator (SOI) structure. One type of SOG is a cross-linked siloxane polymer, preferably of the poly-organo-siloxane type, c... | 05/27/2003 |
| 6559505 | Power integrated circuit with vertical current flow and related manufacturing process Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer ... | 05/06/2003 |
| 6538330 | Multilevel semiconductor-on-insulator structures and circuits Some advanced integrated circuits are fabricated as silicon-on-insulator structures, which facilitate faster operating speeds, closer component spacing, lower power consumption, and so forth. Unfortunately, current bonded-wafer techniques for making such ... | 03/25/2003 |
