Class 257/E21.612 - Complementary vertical transistors (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.611. This subclass
No. of patents: 76
Last issue date: 10/02/2007

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Number	Title	Issue Date
7276754	Annular gate and technique for fabricating an annular gate A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surfac...	10/02/2007
6607960	Bipolar transistor manufacturing method A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a seco...	08/19/2003
6586317	Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage A zener diode is formed in a bipolar or BiCMOS fabrication process by modifying the existing masks that are used in the bipolar or BiCMOS fabrication process, thereby eliminating the need for a separate doping step. In addition, the reverse breakdown volt...	07/01/2003
6573146	Methods of manufacturing complementary bipolar transistors A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral...	06/03/2003
6410395	Method of manufacturing a semiconductor device comprising SiGe HBTs A method of manufacturing a semiconductor device comprising heterojunction bipolar transistors (HBTs), in which method a first semiconductor layer of monocrystalline silicon (5), a second semiconductor layer of monocrystalline silicon comprising 5 to 25 a...	06/25/2002
6404038	Complementary vertical bipolar junction transistors fabricated of silicon-on-sapphire utilizing wide base PNP transistors A method for fabricating complementary vertical bipolar junction transistors of silicon-on-sapphire in fewer steps than required for true complimentary vertical bipolar junction transistors is disclosed. Initially a thin layer of silicon is grown on a sap...	06/11/2002
6337252	Semiconductor device manufacturing method There is provided a method of manufacturing a semiconductor device which can use commonly a part of a step of forming a PAP transistor with a step of forming an NON transistor. In an area separated by a side separation region (5) of PNP formed by doping N...	01/08/2002
6326674	Integrated injection logic devices including injection regions and tub or sink regions A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral...	12/04/2001
6297119	Semiconductor device and its manufacture The present invention discloses a semiconductor device having a PNP bipolar transistor and an NPN bipolar transistor having excellent transistor characteristics formed on the same semiconductor substrate, and a method of manufacturing the semiconductor de...	10/02/2001
6265276	Structure and fabrication of bipolar transistor A complementary bipolar transistor device, made of two separate conductive films such as two highly doped polysilicon films of opposite conductivity types. The doped polysilicon film is used for a base of NPN transistor and an emitter of a PNP transistor ...	07/24/2001
6222250	Bipolar transistor device and method for manufacturing the same A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is ...	04/24/2001
6005283	Complementary bipolar transistors A complementary bipolar transistor having a lateral npn bipolar trasistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral ...	12/21/1999
6005282	Integrated circuit with complementary isolated bipolar transistors Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor...	12/21/1999
5970355	Method for fabricating semiconductor device A method for fabricating a semiconductor device having a base electrode, an emitter electrode, and a collector electrode, includes the steps of: forming first, second, and buried layers in a semiconductor substrate; forming first, second, and third epitax...	10/19/1999
5955775	Structure of complementary bipolar transistors A complementary bipolar transistor device, made of two separate conductive films such as two highly doped polysilicon films of opposite conductivity types. The doped polysilicon film is used for a base of NPN transistor and an emitter of a PNP transistor ...	09/21/1999
5893743	Process of fabricating semiconductor device A process for forming a first bipolar transistor having a single polysilicon structure and a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor on the same substr...	04/13/1999
5885880	Bipolar transistor device and method for manufacturing the same A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is ...	03/23/1999
5763935	Bipolar semiconductor device and fabricating method thereof The bipolar semiconductor device fabricated according to the present invention have high CB junction breakdown voltage (BVCBO), small capacitance between collector and base and high response speed. A n+ type well diffused layer 105 t...	06/09/1998
5759902	Method of making an integrated circuit with complementary junction-isolated bipolar transistors Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and novel chip made by such process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor a...	06/02/1998
5529939	Method of making an integrated circuit with complementary isolated bipolar transistors Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor...	06/25/1996
5411898	Method of manufacturing a complementary bipolar transistor An n type buried layer (2b) lying in the lower part of a PNP transistor (101a) is lower in impurity concentration than an n+ type buried layer (2a) lying in the lower part of an NPN transistor (100). A p+ type buried layer (4a) is f...	05/02/1995
5331198	Semiconductor device including IIL and vertical transistors The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . Th...	07/19/1994
5302848	Integrated circuit with complementary junction-isolated bipolar transistors A process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and a novel chip made by such a process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transi...	04/12/1994
5244821	Bipolar fabrication method A method for forming a bipolar transistor is disclosed. An optional thin screen oxide (.apprxeq.150 Å) may be formed upon a substrate over an already-defined collector region. A BF2 or other implantation is performed through the screen oxide t...	09/14/1993
5219768	Method for fabricating a semiconductor device Selective ion implantation on the respective polysilicon is performed by utilizing a low temperature accelerated oxidation phenomenon in polysilicon with a high impurity concentration and the dependence of an accelerated energy of the impurity projection ...	06/15/1993
5218227	Semiconductor device and method of manufacturing same An n type buried layer (2b) lying in the lower part of a PNP transistor (101a) is lower in impurity concentration than an n+ type buried layer (2a) lying in the lower part of an NPN transistor (100). A p+ type buried layer (4a) is fo...	06/08/1993
5208171	Process for preparing BiCMOS semiconductor device A process for preparing a BiCMOS semiconductor device having a MOS transistor element and a bipolar transistor element both of which are constituted in an epitaxial layer of n-type conductivity formed on a substrate of p-type conductivity, which comprises...	05/04/1993
5162252	Method of fabricating IIL and vertical complementary bipolar transistors The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1). The...	11/10/1992
5151382	Method of manufacturing a semiconductor device by maskless pn junction isolation means A semiconductor body (1 ) is provided having a first region (4) of one conductivity type adjacent one major surface (2). An insulating layer (5) is formed on the one major surface and masking means (6,7) are used to form over first and second areas (20 an...	09/29/1992
5151378	Self-aligned planar monolithic integrated circuit vertical transistor process A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isol...	09/29/1992
5137838	Method of fabricating P-buried layers for PNP devices A P-type buried layer is described for use with planar, silicon, monolithic, epitaxial, PN junction-isolated transistors of PNP conductivity primarily for use in IC construction. The buried layer includes a high concentration of boron and gallium along wi...	08/11/1992
5132234	Method of producing a bipolar CMOS device A method of producing a bipolar CMOS device for providing a unipolar CMOS transistor with a polysilicon gate and a self-aligned NPN and VPNP transistor on a same chip, so that a high performance analog and digital BiCMOS device can be realized....	07/21/1992
5128272	Self-aligned planar monolithic integrated circuit vertical transistor process A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isol...	07/07/1992
5119157	Semiconductor device with self-aligned contact to buried subcollector A P- semiconductor material substrate which has been ion-implanted with N-type dopants to form an N+ subcollector layer is annealed in Argon to further remove implant damage and drive the dopant ions deeper into the P substrate. Next a lightly doped N- ep...	06/02/1992
5110749	Method for manufacturing semiconductor device A p-type buried layer is formed on the surface of an n-type semiconductor substrate directly or on the surface of an n-type semiconductor region with relatively low impurity concentration which is formed on the surface of the semiconductor substrate. In t...	05/05/1992
5066602	Method of making semiconductor IC including polar transistors In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in th...	11/19/1991
5065214	Integrated circuit with complementary junction-isolated bipolar transistors An integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, is disclosed. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the s...	11/12/1991
5055418	Process for fabricating complementary contactless vertical bipolar transistors A complementary NPN and PNP contactless vertical transistor structure is formed by a process that includes the steps of providing: (1) a buried layer and P-- tub for NPN; (2) a channel stopper for NPN, and a buried layer for PNP; (3) isolation oxide for N...	10/08/1991
5014107	Process for fabricating complementary contactless vertical bipolar transistors A complementary NPN and PNP contactless vertical transistor structure is formed by a process that includes the steps of providing: (1) a buried layer and P- tub for NPN; (2) a channel stopper for NPN, and a buried layer for PNP; (3) isolation oxide for NP...	05/07/1991
5011784	Method of making a complementary BiCMOS process with isolated vertical PNP transistors A BiCMOS process which provides both isolated and vertical NPN and PNP transistors with better performance characteristics and fewer additional steps than the prior art. The additional steps consist of masked implants with no changes in the thermal steps ...	04/30/1991

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Class 257/E21.612 - Complementary vertical transistors (EPO)