Bizarre Patents
A Receptacle for supporting, rotating and sculpting a portion of ice cream or similarly malleable food while it is being consumed.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7442644 | Method for manufacturing nitride semiconductor wafer or nitride semiconductor device; nitride semiconductor wafer or nitride semiconductor device made by the same; and laser irradiating apparatus used for the same To remove the disparate substrate from nitride semiconductor layer grown over the disparate substrate, that is made of a material different from nitride semiconductor, by irradiating the disparate substrate with laser beam having a wavelength shorter than the band g... | 10/28/2008 |
| 7435679 | Alloyed underlayer for microelectronic interconnects Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during... | 10/14/2008 |
| 7432198 | Semiconductor devices and methods of forming interconnection lines therein An example disclosed semiconductor device includes a semiconductor substrate, a lower interlayer insulating layer formed on the substrate, a lower wire formed on the lower interlayer insulating layer, and an upper interlayer insulating layer which is formed on the l... | 10/07/2008 |
| 7382042 | COF flexible printed wiring board and method of producing the wiring board The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, and which exhibits no drop in bonding strength during panel bonding carried out after mounting of semiconductor chips, whereby reliabilit... | 06/03/2008 |
| 7319052 | Alloying method, and wiring forming method, display device forming method, and image display unit fabricating method An alloying method includes the steps of forming a metal layer on a semiconductor having been transferred to a material having a low thermal conductivity, and alloying an interface between the semiconductor and the metal layer by irradiating the interface with a las... | 01/15/2008 |
| 7307018 | Method of fabricating conductive lines A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In... | 12/11/2007 |
| 7279380 | Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method A method of fabricating a chalcogenide memory cell is described. The cross-sectional area of a chalcogenide memory element within the cell is controlled by the thickness of a bottom electrode and the width of a word line. The method allows the formation of ultra sma... | 10/09/2007 |
| 7229917 | Film formation method and apparatus for semiconductor process A film-formation method for a semiconductor process includes seed film formation and main film formation. In the seed film formation, a metal-containing raw material gas and a first assist gas to react therewith are supplied into a process container, which accommoda... | 06/12/2007 |
| 7198989 | Method of producing a COF flexible printed wiring board The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, to thereby enhance reliability and productivity of a semiconductor chip mounting line, and also provides a method of producing the COF fl... | 04/03/2007 |
| 7183209 | Semiconductor device and manufacturing method thereof The semiconductor device fabrication method of the present invention includes forming metal wirings on a semiconductor substrate, forming a first blocking layer on the semiconductor substrate and the metal wiring, forming a first FSG on the first blocking layer, for... | 02/27/2007 |
| 7154180 | Electronic device, method of manufacture of the same, and sputtering target In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film ... | 12/26/2006 |
| 7098539 | Electronic device, method of manufacture of the same, and sputtering target In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film ... | 08/29/2006 |
| 6690092 | Multilayer interconnection structure of a semiconductor device In order to solve the aforementioned problems, the present invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is form... | 02/10/2004 |
| 6679951 | Metal anneal with oxidation prevention The invention relates generally to the prevention of copper oxidation during copper anneal processes. In one aspect of the invention, copper oxidation is prevented by carrying out the anneal in the presence of one or more organic reducing agents.... | 01/20/2004 |
| 6673704 | Semiconductor device and method of manufacturing the same A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, fillin... | 01/06/2004 |
| 6660634 | Method of forming reliable capped copper interconnects The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlo... | 12/09/2003 |
| 6657303 | Integrated circuit with low solubility metal-conductor interconnect cap An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer ha... | 12/02/2003 |
| 6656836 | Method of performing a two stage anneal in the formation of an alloy interconnect A method of performing a two stage anneal in the formation of an alloy interconnect can include forming a via aperture in a dielectric layer where the via aperture provides an area for formation of a via, providing a seed layer along lateral side walls of... | 12/02/2003 |
| 6650017 | Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate a... | 11/18/2003 |
| 6649499 | Method of varying the resistance along a conductive layer A method for varying the resistance along a conductive layer. The method including the step of removing at least a portion of a resistance-altering constituent diffused within the conductive layer.... | 11/18/2003 |
| 6646346 | Integrated circuit metallization using a titanium/aluminum alloy An integrated circuit metallization structure using a titanium/aluminum alloy, and a method to generate such a structure, provide reduced leakage current by allowing mobile impurities such as water, oxygen, and hydrogen to passivate structural defects in ... | 11/11/2003 |
| 6638580 | Apparatus and a method for forming an alloy layer over a substrate using an ion beam One embodiment of the invention involves introducing at least two metals into a chamber for forming an alloy layer over a substrate. This is accomplished by a variety of methods. In one embodiment, at least two metals are mixed and introduced into a chamb... | 10/28/2003 |
| 6633085 | Method of selectively alloying interconnect regions by ion implantation A metal interconnect structure and method of making the same implants ions of an alloy elements into a copper line through a via. Then ion implantation of the alloy elements in the copper line through the via provides improved electromigration properties ... | 10/14/2003 |
| 6627538 | Focused ion beam deposition Introducing at least one metal such as cobalt, molybdenum, metal carbonyl, tungsten, platinum, or other suitable metal to a focused ion beam. Introducing the focused ion beam to a substrate within a processing chamber. Forming at least one layer over a su... | 09/30/2003 |
| 6624075 | Method of reducing electromigration in a copper line by Zinc-Doping of a copper surface from an electroplated copper-zinc alloy thin film and a semiconductor device thereby formed A method of reducing electromigration in copper interconnect lines by restricting Cu-diffusion pathways along a Cu surface via doping the Cu surface with Zn from an interim copper-zinc alloy (Cu--Zn) thin film electroplated on the copper (Cu) surface from... | 09/23/2003 |
| 6617689 | Metal line and method of suppressing void formation therein An interconnect line that is enclosed within electrically conductive material is disclosed. The interconnect line, which is useful for electrically connecting devices in an integrated circuit, is defined by an aluminum layer having a bottom surface covere... | 09/09/2003 |
| 6613671 | Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby A conductive connection forming method includes forming a first layer including a first metal on a substrate and forming a second layer including a second metal different from the first metal on the first layer. At least a part of the first layer may be t... | 09/02/2003 |
| 6607978 | Method of making a semiconductor device with alloy film between barrier metal and interconnect Between a copper film 5a and a tantalum-based barrier metal film 2b, there is set an alloy layer 10 made through the reaction of the material of the barrier metal film and copper.... | 08/19/2003 |
| 6597009 | Reduced contact area of sidewall conductor A method including, in a dielectric material over a contact on a substrate, forming a trench to the contact; introducing an electrode material along the sidewalls of the trench; introducing a phase change material over material along a first sidewall; and... | 07/22/2003 |
| 6534815 | Semiconductor device with stack electrode formed using HSG growth A semiconductor memory device includes an interlayer insulating film, a contact film, a crystallization preventing film and a conductive film. The interlayer insulating film is formed on a semiconductor substrate to cover a source/drain region of a MOS tr... | 03/18/2003 |
| 6521523 | Method for forming selective protection layers on copper interconnects Disclosed is a method for forming selective protection layers on copper interconnects in a damascene process. A copper layer is deposited overlying a dielectric layer and filling interconnect trenches which are previously formed in the dielectric layer. T... | 02/18/2003 |
| 6515367 | Sub-cap and method of manufacture therefor in integrated circuit capping layers An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device diele... | 02/04/2003 |
| 6511910 | Method for manufacturing semiconductor devices A semiconductor device includes a semiconductor substrate having a device element, an interlayer dielectric layer (silicon oxide layer, BPSG layer) formed on the semiconductor substrate, a through hole defined in the interlaver dielectric layer, a barrier... | 01/28/2003 |
| 6509263 | Method for fabricating a semiconductor memory device having polysilicon with an enhanced surface concentration and reduced contact resistance A method for fabricating a semiconductor device to reduce the contact resistance by enhancing the surface concentration of doped polysilicon in a semiconductor substrate divided into active and field regions, comprises the steps of forming a plurality of ... | 01/21/2003 |
| 6504224 | Methods and structures for metal interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and th... | 01/07/2003 |
| 6492266 | Method of forming reliable capped copper interconnects The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlo... | 12/10/2002 |
| 6492261 | Focused ion beam metal deposition Introducing at least one metal such as cobalt, molybdenum, metal carbonyl, tungsten, platinum, or other suitable metal to a focused ion beam. Introducing the focused ion beam to a substrate within a processing chamber. Forming at least one layer over a su... | 12/10/2002 |
| 6492735 | Semiconductor device with alloy film between barrier metal and interconnect Between a copper film 5a and a tantalum-based barrier metal film 2b, there is set an alloy layer 10 made through the reaction of the material of the barrier metal film and copper.... | 12/10/2002 |
| 6486026 | Method of forming DRAM circuitry The invention comprises integrated circuitry fabrication methods of making a conductive electrical connection, methods of forming a capacitor and an electrical connection thereto, methods of forming DRAM circuitry, integrated circuitry, and DRAM integrate... | 11/26/2002 |
| 6482740 | Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH This invention relates to manufacturing of integrated circuits (ICs) and especially conductive layers suitable for use in an IC. According to the preferred method a metal oxide thin film is deposited on a substrate surface and reduced thereafter essential... | 11/19/2002 |
