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| Number | Title | Issue Date |
| 7394028 | Flexible circuit substrate for flip-chip-on-flex applications A circuit substrate for attachment to an integrated circuit chip comprises an electrical trace, a mounting pad and a dielectric layer. The mounting pad has a first surface, one or more sidewalls and a second surface. The first surface is attached to the electrical t... | 07/01/2008 |
| 7378338 | Method of forming an interconnect structure diffusion barrier with high nitrogen content In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm. ... | 05/27/2008 |
| 7358188 | Method of forming conductive metal silicides by reaction of metal with silicon The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a ni... | 04/15/2008 |
| 7348270 | Techniques for forming interconnects A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect m... | 03/25/2008 |
| 7329602 | Wiring structure for integrated circuit with reduced intralevel capacitance A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated fr... | 02/12/2008 |
| 7329563 | Method for fabrication of wafer level package incorporating dual compliant layers A method is provided for forming wafer level package that incorporates dual compliant layers and a metal cap layer on top of I/O pads. The wafer level package includes a plurality of metal cap layers formed on top of a plurality of I/O pads to function as stress buf... | 02/12/2008 |
| 7326610 | Process options of forming silicided metal gates for advanced CMOS devices Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielec... | 02/05/2008 |
| 7316958 | Masks for fabricating semiconductor devices and methods of forming mask patterns Masks for fabricating a semiconductor device and methods of forming mask patterns are provided which are capable of enhancing the breakdown voltage of the fabricated semiconductor device by accurately correcting a line width pattern error of a semiconductor substrat... | 01/08/2008 |
| 7271086 | Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In one embodiment, a method includes constructing a dielectric structure on a microfeature workpiece having a ... | 09/18/2007 |
| 7265405 | Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines.... | 09/04/2007 |
| 7262125 | Method of forming low-resistivity tungsten interconnects Methods and apparatus for preparing a low-resistivity tungsten film on a substrate are provided. Methods involve the formation of a tungsten nucleation layer on a substrate using pulsed nucleation layer (PNL) techniques and depositing a bulk tungsten layer thereon. ... | 08/28/2007 |
| 7259083 | Local interconnect manufacturing process The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The fi... | 08/21/2007 |
| 7247562 | Semiconductor element, semiconductor device and methods for manufacturing thereof The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield ... | 07/24/2007 |
| 7217653 | Interconnects forming method and interconnects forming apparatus The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production o... | 05/15/2007 |
| 7208404 | Method to reduce Rs pattern dependence effect A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 ... | 04/24/2007 |
| 7183188 | Method for fabricating contact-making connections The invention provides a method for fabricating contact-making connections, having the steps of: a) providing a substrate (101) with electronic circuit units (102a, 102b) arranged thereon, an intermediate layer (103) filling... | 02/27/2007 |
| 7176554 | Methods for producing a semiconductor entity A method for producing a semiconductor entity is described. The method includes providing a donor substrate having a zone of weakness at a predetermined depth to define a thin layer, and the donor substrate includes a bonding interface. A receiver substrate is also ... | 02/13/2007 |
| 7173338 | Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electri... | 02/06/2007 |
| 7160737 | Method for fabricating semiconductor device A material of low viscosity is applied to a ferroelectric film 32 formed by MOCVD to form a buried layer 34. Then, anisotropic etching is made on the entire surface to remove the tops of convexities on the surface of the ferroelectric film 32, a... | 01/09/2007 |
| 7138716 | Addition of metal layers with signal reallocation to a microprocessor for increased frequency and lower power A semiconductor device and method of adding metal layers in a semiconductor device with signal reallocation are disclosed. The device has a first layer with a plurality of signal wires. A second layer adjacent to the first layer is also included that has a plurality... | 11/21/2006 |
| 7119005 | Semiconductor local interconnect and contact An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spac... | 10/10/2006 |
| 7109068 | Through-substrate interconnect fabrication methods A method for forming a conductive via or through-wafer interconnect (TWI) in a semiconductive substrate for use as a contact card, test connector, semiconductor package interposer, or die interconnect includes the acts of (a) forming an oxide or nitride layer on bot... | 09/19/2006 |
| 7094687 | Reduced dry etching lag A method of forming via structures between a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is formed, and a dielectric layer is formed over the first electrically conductive layer. A first pho... | 08/22/2006 |
| 6703668 | Local interconnect formed using silicon spacer A local interconnect structure that includes a silicon spacer. After deposition of polysilicon gates and formation of spacers on a semiconductor substrate, photolithography and oxide etch steps are performed to remove a portion of a spacer along a segment... | 03/09/2004 |
| 6700205 | Semiconductor devices having contact plugs and local interconnects Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are comp... | 03/02/2004 |
| 6699726 | Semiconductor device and method for the manufacture thereof The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the s... | 03/02/2004 |
| 6700211 | Method for forming conductors in semiconductor devices A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby ... | 03/02/2004 |
| 6699751 | Method of fabricating a capacitor for semiconductor devices A method of fabricating a capacitor in semiconductor devices includes forming an insulating interlayer on a semiconductor substrate; forming a contact hole in the insulating interlayer to expose a portion of the semiconductor substrate; forming a plug in ... | 03/02/2004 |
| 6696732 | Semiconductor device having S/D to S/D connection and isolation region between two semiconductor elements A plurality of MOS type FET devices 14 and 16 are provided on a semiconductor substrate 12. A lower interlayer insulating film 20 is provided thereon. Each of through holes 22, which extends from each of gate electrodes 14c of the plural FET devices via s... | 02/24/2004 |
| 6696722 | Storage node of DRAM cell A storage node of a DRAM cell capacitor includes a first insulating layer in which a bit line pattern is formed, a second insulating layer formed on the first insulating layer of which material is different from that of the second insulating layer, a firs... | 02/24/2004 |
| 6693025 | Local interconnect structures for integrated circuits and methods for making the same A method for making a flexible metal silicide local interconnect structure. The method includes forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon... | 02/17/2004 |
| 6693335 | Semiconductor raised source-drain structure A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the d... | 02/17/2004 |
| 6689654 | Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region an... | 02/10/2004 |
| 6689655 | Method for production process for the local interconnection level using a dielectric conducting pair on pair The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying... | 02/10/2004 |
| 6686633 | Semiconductor device, memory cell, and processes for forming them A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at lea... | 02/03/2004 |
| 6686636 | Semiconductor raised source-drain structure A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication wi... | 02/03/2004 |
| 6683355 | Semiconductor raised source-drain structure A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication wi... | 01/27/2004 |
| 6683339 | Semiconductor memory device having metal contact structure The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.... | 01/27/2004 |
| 6680538 | Semiconductor device for suppressing detachment of conductive layer A semiconductor device and a method for manufacturing the semiconductor device are provided in which a lower plug electrically connected with an active region of a wafer has a recession, and a conductive layer has a projection fitted into the recession of... | 01/20/2004 |
| 6680514 | Contact capping local interconnect A method and structure for forming a metallic capping interface between damascene conductive wires/studs and damascene conductive wiring line structures. The method forms a first insulative layer on a substrate layer, followed by forming damascene conduct... | 01/20/2004 |
