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| Number | Title | Issue Date |
| 7338867 | Semiconductor device having contact pads and method for manufacturing the same Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. S... | 03/04/2008 |
| 7291566 | Barrier layer for a processing element and a method of forming the same In order to mitigate erosion of exposed processing elements in a processing system by the process and any subsequent contamination of the substrate in the processing system, processing elements exposed to the process are coated with a protective barrier. The protect... | 11/06/2007 |
| 7223627 | Memory element and its method of formation A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin metal containing layer having a thickness of less than about 250 Angstroms over a second chalcogenide glass... | 05/29/2007 |
| 7195989 | Electrochemical fabrication methods using transfer plating of masks Three-dimensional structures are electrochemically fabricated by depositing a first material onto previously deposited material through voids in a patterned mask where the patterned mask is at least temporarily adhered to a substrate or previously formed layer of ma... | 03/27/2007 |
| 7170176 | Semiconductor device A technology for easily forming a multi-layer wiring structure that is fine and reliable. In the multi-layer wiring structure, the lower-layer wiring and the upper-layer wiring that are formed to sandwich an insulating layer are electrically connected to each other ... | 01/30/2007 |
| 6693028 | Semiconductor device having multilayer wiring structure and method for manufacturing the same A method for manufacturing a semiconductor device includes a step of forming a first groove in a first insulating film, forming a conductive film in the first groove, a step of selectively forming a second insulating film on the conductive film and the fi... | 02/17/2004 |
| 6690077 | Antireflective coating and field emission display device, semiconductor device and wiring line comprising same Titanium aluminum nitrogen ("Ti--Al--N") is deposited onto a semiconductor substrate area to serve as an antireflective coating. For wiring line fabrication processes, the Ti--Al--N layer serves as a cap layer which prevents unwanted reflection of photoli... | 02/10/2004 |
| 6690093 | Metal contact structure in semiconductor device and method for forming the same A metal contact structure of a semiconductor device and a method for forming the same, wherein an upper conductive layer is formed by etching a metal layer, which fills a contact hole and is formed on the entire surface of an interlayer dielectric film an... | 02/10/2004 |
| 6682999 | Semiconductor device having multilevel interconnections and method of manufacture thereof The present invention provides, in one aspect, a method for fabricating an interconnect system within a semiconductor device. In this particular embodiment, the method comprises forming a conductive layer over a substrate of the semiconductor device, such... | 01/27/2004 |
| 6680514 | Contact capping local interconnect A method and structure for forming a metallic capping interface between damascene conductive wires/studs and damascene conductive wiring line structures. The method forms a first insulative layer on a substrate layer, followed by forming damascene conduct... | 01/20/2004 |
| 6680511 | Integrated circuit devices providing improved short prevention The present invention provide integrated circuit devices and methods of fabricating the same that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer... | 01/20/2004 |
| 6670271 | Growing a dual damascene structure using a copper seed layer and a damascene resist structure The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown from a seed layer to substantially fill openings in a two layer structure wherein the two layers are independently either d... | 12/30/2003 |
| 6664197 | Process for etching thin-film layers of a workpiece used to form microelectronic circuits or components A process for removing at least one thin-film layer from a surface of a workpiece pursuant to manufacturing a microelectronic interconnect or component is set forth. Generally stated, the process comprises the oxidation of at least a portion of the at lea... | 12/16/2003 |
| 6660625 | Method of electroless plating copper on nitride barrier A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line... | 12/09/2003 |
| 6656814 | Methods of fabricating integrated circuit devices including distributed and isolated dummy conductive regions An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines ... | 12/02/2003 |
| 6656833 | Method of DRAM A semiconductor device is fabricated by forming a first insulating layer, in which an etch stopper and a first contact plug are formed so that the etch stopper surrounds an end portion of the first contact plug and the latter extends through the first ins... | 12/02/2003 |
| 6653218 | Method of fabricating resin-encapsulated semiconductor device A polyimide layer is formed over a semiconductor chip, a rewiring to be connected to each of the electrode pads of the semiconductor chip is formed over the polyimide layer, and a post serving as a terminal is connected to each of the electrode pads via t... | 11/25/2003 |
| 6635563 | Method of manufacturing semiconductor device Precisely forming a fine resist pattern on a stopper film of silicon nitride, in a method of manufacturing a multi-layer interconnection structure which uses the stopper film. A silicon nitride film forming step is a step to select a thickness of a silico... | 10/21/2003 |
| 6635564 | Semiconductor structure and method of fabrication including forming aluminum columns High aspect ratio vias formed in a first insulating layer covering a semiconductor substrate (body) are filled with conductors in a manner that both reduces the number of processing steps and allows an alignment tool (stepper) to align to alignment and ov... | 10/21/2003 |
| 6627523 | Method of forming a metal wiring in a semiconductor device There is disclosed a method of forming a metal wiring in a semiconductor device. The method includes forming a seed layer on a semiconductor substrate in which given structures including a lower metal wiring are formed, forming a photosensitive film patte... | 09/30/2003 |
| 6627537 | Bit line and manufacturing method thereof A method for manufacturing a bit line is disclosed. Such a method includes: forming a layer-insulation layer on the surface of a semiconductor substrate; forming a contact hole on a predetermined region of the layer-insulation layer; forming a first condu... | 09/30/2003 |
| 6623912 | Method to form the ring shape contact to cathode on wafer edge for electroplating in the bump process when using the negative type dry film photoresist A method of clearing photoresist on a wafer edge, including the following steps. A wafer having a upper exposed conductive layer is provided. The wafer having a center, an edge and a ring-shaped area proximate the wafer edge. A photoresist layer is formed... | 09/23/2003 |
| 6624501 | Capacitor and semiconductor device A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second... | 09/23/2003 |
| 6624063 | Semiconductor device having low dielectric layer and method of manufacturing thereof A semiconductor device including a semiconductor substrate, an insulating layer formed on the substrate, a dielectric organic layer formed on the insulating layer and having a dielectric constant of not more than 3.0, and an interconnection layer in conta... | 09/23/2003 |
| 6624525 | Contact plug in capacitor device A semiconductor device comprises a first insulating film formed over a semiconductor substrate, a second insulating film formed on the first insulating film, a contact plug made of a conductive material vertically penetrating the first and second insulati... | 09/23/2003 |
| 6617689 | Metal line and method of suppressing void formation therein An interconnect line that is enclosed within electrically conductive material is disclosed. The interconnect line, which is useful for electrically connecting devices in an integrated circuit, is defined by an aluminum layer having a bottom surface covere... | 09/09/2003 |
| 6611010 | Semiconductor device In a bit line contact section, a contact hole is formed through a silicon oxide film, and a contact plug made of a polysilicon film doped with impurities is buried in the contact hole. The silicon oxide film is formed with a wiring groove overlapping the ... | 08/26/2003 |
| 6605525 | Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks as stress buffering layer and package formed are described. The method incorporates the step of forming metal lines in-between the plurality of IC dies on a wafe... | 08/12/2003 |
| 6602653 | Conductive material patterning methods A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are conve... | 08/05/2003 |
| 6602789 | Method of forming a metal line in a semiconductor memory device A preferred method of forming a metal line in a semiconductor memory device includes depositing first, second, and third metal layers on a semiconductor substrate. A fourth layer is deposited on the third metal layer. The fourth layer is etched to form a ... | 08/05/2003 |
| 6602773 | Methods of fabricating semiconductor devices having protected plug contacts and upper interconnections Embodiments of methods of fabricating protected contact plugs include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming an electrically conductive lower barrier layer that lines at least ... | 08/05/2003 |
| 6600207 | Structure to reduce line-line capacitance with low K material A structure to reduce line--line capacitance using low dielectric constant (K) materials is provided. Embodiments in accordance with the present invention are semiconductor devices having a single level of interconnection as well as semiconductor devices ... | 07/29/2003 |
| 6599809 | Method of manufacturing semiconductor device having a marking recess A semiconductor device capable of preventing yield reduction and a method of manufacturing the same can be obtained. The method of manufacturing a semiconductor device including an element formation region arranged on a semiconductor substrate and an exte... | 07/29/2003 |
| 6589816 | Method of forming metal connection elements in integrated circuits A method of forming metal connection elements in integrated circuits formed on adjacent areas of a wafer includes forming a conductive seed layer on a substrate of the wafer. A first mask covers the integrated circuits and leaves exposed areas of the seed... | 07/08/2003 |
| 6573598 | Semiconductor device and method of fabricating the same A semiconductor device is disclosed which includes a semiconductor chip having a plurality of electrode pads on its upper surface; terminals such as copper posts formed on the upper surface of the semiconductor chip, and electrically connected to each of ... | 06/03/2003 |
| 6566701 | Encapsulated conductive pillar The present invention provides an encapsulated 3-D conductive pillar and a method of formation thereof. Significant economic savings are achieved by filling a substantial portion of the volume of the pillar with a lesser expensive conductive material. Add... | 05/20/2003 |
| 6564812 | Alkanolamine semiconductor process residue removal composition and process A two carbon atom linkage alkanolamine compound composition comprises the two carbon atom linkage alkanolamine compound, gallic acid or catechol, and optionally, an aqueous hydroxylamine solution. The balance of the composition is made up of water, prefer... | 05/20/2003 |
| 6562732 | Method of manufacturing a semiconductor device The invention relates to a method of manufacturing a semiconductor device, comprising the provision of a dual damascene structure (20). This dual damascene structure (20) comprises a metal layer (1) with thereon a first dielectric layer (2) provided with ... | 05/13/2003 |
| 6555204 | Method of preventing bridging between polycrystalline micro-scale features A method of preventing or at least reducing the likelihood of bridging between adjacent micro-scale polycrystalline structures, and particularly to reducing electrical shorting between adjacent metallization lines of a microcircuit. The method generally e... | 04/29/2003 |
| 6546939 | Post clean treatment A composition for removal of chemical residues from metal or dielectric surfaces or for chemical mechanical polishing of a copper or aluminum surface is an aqueous solution with a pH between about 3.5 and about 7. The composition contains a monofunctional... | 04/15/2003 |
