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| Number | Title | Issue Date |
| 7400045 | Semiconductor device and method for fabricating the same In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper... | 07/15/2008 |
| 7381638 | Fabrication technique using sputter etch and vacuum transfer First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the... | 06/03/2008 |
| 7364928 | Electro-optical device and method of manufacturing the same, element driving device and method of manufacturing the same, element substrate, and electronic apparatus In a circuit to drive driven elements such, as electro-optical elements, an electro-optical device has an element layer, a wire-forming layer, and an electronic component layer in order to suppress variation in characteristics of active elements. The element layer h... | 04/29/2008 |
| 7329602 | Wiring structure for integrated circuit with reduced intralevel capacitance A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated fr... | 02/12/2008 |
| 7320900 | Method of manufacturing liquid crystal display panels Before cutting a gang-printed substrate having a multiplicity of liquid crystal display panel regions provided thereon into individual liquid crystal display panels, a voltage is applied to all of the multiplicity of liquid crystal display panel regions to inspect d... | 01/22/2008 |
| 7309649 | Method of forming closed air gap interconnects and structures formed thereby A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remai... | 12/18/2007 |
| 7229873 | Process for manufacturing dual work function metal gates in a microelectronics device The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stack... | 06/12/2007 |
| 7214603 | Method for fabricating interconnect structures with reduced plasma damage Methods to form interconnect structures utilizing sacrificial filling material layers are described herein. Utilizing the sacrificial filling material makes it possible to reduce damage to interlayer dielectric layers that result in enhanced device performance and/o... | 05/08/2007 |
| 6699396 | Methods for electroplating large copper interconnects A method for forming conductive features in dielectric materials is disclosed which includes providing a dielectric layer and forming a release layer over the dielectric layer. Then a feature is defined into the each of the release layer and the dielectri... | 03/02/2004 |
| 6649510 | Method of forming semiconductor memory device using a double layered capping pattern A method of forming a semiconductor memory device using a double layered capping pattern and a semiconductor memory device formed thereby are provided. A plurality of interconnection patterns are formed on a semiconductor substrate. Each of the interconne... | 11/18/2003 |
| 6583053 | Use of a sacrificial layer to facilitate metallization for small features A method of fabricating a copper interconnect using a sacrificial layer. A SiC layer (106) is formed over the dielectric layer (102). A sacrificial layer (108) is formed over the SiC layer (106). A trench (112) is etched in the sacrificial layer (108), th... | 06/24/2003 |
| 6559045 | Fabrication of integrated circuits with borderless vias The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second die... | 05/06/2003 |
| 6486559 | COPPER WIRING STRUCTURE COMPRISING A COPPER MATERIAL BURIED IN A HOLLOW OF AN INSULATING FILM AND A CARBON LAYER BETWEEN THE HOLLOW AND THE COPPER MATERIAL IN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME The object of the present invention is to provide a copper wiring structure in which finely processed copper wiring in a wiring structure in grooves is steadily formed with a high reliability and a method for fabricating the same, wherein an electroconduc... | 11/26/2002 |
| 6482741 | COPPER WIRING STRUCTURE COMPRISING A COPPER MATERIAL BURIED IN A HOLLOW OF AN INSULATING FILM AND A CARBON LAYER BETWEEN THE HOLLOW AND THE COPPER MATERIAL IN SEMICONDUCTOR DEVICE AND METHOD FABRICATING THE SAME The object of the present invention is to provide a copper wiring structure in which finely processed copper wiring in a wiring structure in grooves is steadily formed with a high reliability and a method for fabricating the same, wherein an electroconduc... | 11/19/2002 |
| 6452275 | Fabrication of integrated circuits with borderless vias The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second die... | 09/17/2002 |
| 6426289 | Method of fabricating a barrier layer associated with a conductor layer in damascene structures The present invention is directed to a simplified, CVD-less method of forming a barrier layer for a metal layer which prevents metal contamination in an integrated circuit. The invention utilizes a sacrificial multilayer dielectric structure and selective... | 07/30/2002 |
| 6423567 | Method for producing contact structures in solar cells The present invention relates to a process for the fabrication of contact structures in semiconductor components, in particular, solar cells, such as semiconductor components having such contact structures. According to one aspect of the present invention, aft... | 07/23/2002 |
| 6420262 | Structures and methods to enhance copper metallization Structures and methods are described that inhibit atomic migration which otherwise creates an undesired capacitive-resistive effect arising from a relationship between a metallization layer and an insulator layer of a semiconductor structure. A layer of a... | 07/16/2002 |
| 6403996 | Semiconductor memory device using double layered capping pattern and semiconductor memory device formed thereby A method of forming a semiconductor memory device using a double layered capping pattern and a semiconductor memory device formed thereby are provided. A plurality of interconnection patterns are formed on a semiconductor substrate. Each of the interconne... | 06/11/2002 |
| 6355555 | Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer A method is provided for forming a copper interconnect, the method including forming a sacrificial dielectric layer above a structure layer, forming an opening in the sacrificial dielectric layer and forming a copper layer above the sacrificial dielectric... | 03/12/2002 |
| 6245655 | Method for planarized deposition of a material A method for selective deposition of a material, such as copper, to form planarized inlaid device interconnect structures, the method suppressing deposition of the material at other than the defined interconnect inlaid metal line trenches and via plug hol... | 06/12/2001 |
| 6156651 | Metallization method for porous dielectrics This is a method of forming mechanically robust vias and entrenched conductors on a dielectric layer (which dielectric layer is on an electronic microcircuit substrate which vias and entrenched conductors are electrically connected to a conductive area on... | 12/05/2000 |
| 6150260 | Sacrificial stop layer and endpoint for metal CMP A new method of metal plug metallization utilizing a sacrificial layer as a CMP stop to protect the oxide layer from damage during CMP is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer cove... | 11/21/2000 |
| 6146986 | Lithographic method for creating damascene metallization layers An improved method of forming a metallization layer in a layer stack is disclosed. In one aspect of the invention, a method of performing a lithographic damascene etch on a layer stack to form a metal line is disclosed. The layer stack, which is disposed ... | 11/14/2000 |
| 6121150 | Sputter-resistant hardmask for damascene trench/via formation The dimensional precision and accuracy of sub-micron-sized, in-laid metallization patterns, e.g., of electroplated copper or copper alloy, formed in the surface of a dielectric layer are significantly improved by utilizing a layer of a sputter-resistant m... | 09/19/2000 |
| 6117782 | Optimized trench/via profile for damascene filling In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improved reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments i... | 09/12/2000 |
| 6103455 | Method to form a recess free deep contact A method of forming a deep contact by forming a dielectric layer 20 over a semiconductor structure 10. A main point is that the hard mask 30 is removed after the plug 52 is formed. A hard mask layer 30 is formed over the dielectric layer 20. A contact pho... | 08/15/2000 |
| 6090700 | Metallization method for forming interconnects in an integrated circuit A metallization method for forming contact studs and via plugs is disclosed. The method includes: patterning first conductive contacts over a substrate; forming a first dielectric layer over the first conductive contacts and the substrate; forming a sacri... | 07/18/2000 |
| 6087256 | Method for manufacturing modified T-shaped gate electrode In a method for manufacturing a semiconductor device, an insulating layer is formed on a semiconductor substrate, and a refractory metal is formed layer on the insulating layer. Then, a first opening is perforated in the refractory metal layer, and a part... | 07/11/2000 |
| 6064084 | Semiconductor device having a reliable contact structure A fabrication process of a semiconductor device includes a step of forming a conductive overhang structure at a top part of a contact hole in continuation with a thin conductive film covering an exposed bottom surface and an inner surface of said contact ... | 05/16/2000 |
| 6040242 | Method of manufacturing a contact plug There is provided a method of manufacturing a semiconductor device, comprising steps of forming an insulating film on a semiconductor substrate; forming a first film of a first material to cover the insulating film; forming a contact-hole through the insu... | 03/21/2000 |
| 6001739 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device comprising the steps of forming an organic insulating film of a low dielectric constant on a surface of a silicon wafer, forming a photoresist film on the organic insulating film, exposing the photoresist f... | 12/14/1999 |
| 5895271 | Metal film forming method A metal film forming method by which a metal film having a desired pattern can be formed with good reproducibility and satisfactory precision. In a metal film forming method for forming a metal film into the desired pattern on a surface of an object by th... | 04/20/1999 |
| 5891804 | Process for conductors with selective deposition This is a method of forming a conductor 26 on an interlevel dielectric layer 12 which is over an electronic microcircuit substrate 10, and the structure produced thereby. The method utilizes: forming an intralevel dielectric layer 14 over the interlevel d... | 04/06/1999 |
| 5888892 | Metal layer pattern forming method Disclosed is a metal layer pattern forming method which easily allows lift-off. The thickness of the photoresist layer is not less than double the thickness of the metal layer, and the maximum temperature that the surface of the substrate to be processed ... | 03/30/1999 |
| 5821603 | Method for depositing double nitride layer in semiconductor processing Methods for depositing a nitride layer on a surface of an integrated circuit wafer for protecting against over etching during subsequent etching of overlying layers. A first nitride deposition method utilizes a chemical vapor deposition process having a v... | 10/13/1998 |
| 5766808 | Process for forming multilayer lift-off structures A process is disclosed for forming multilayered polyimide structure from negative photosensitive polyimide precursors. An initial polyimide layer is deposited and imagewise exposed. The unexposed portions of the initial polyimide layer are inhibited and t... | 06/16/1998 |
| 5503961 | Process for forming multilayer lift-off structures A process is disclosed for forming multilayered polyimide structure from negative photosensitive polyimide precursors. An initial polyimide layer is deposited and imagewise exposed. The unexposed portions of the initial polyimide layer are inhibited and t... | 04/02/1996 |
| 5434451 | Tungsten liner process for simultaneous formation of integral contact studs and interconnect lines Tungsten studs and tungsten lined studs that make low resistance thermally stable ohmic or Schottky contacts to active devices on a semiconductor substrate are made by first defining a triplex metallurgical structure. The triplex metallurgical structure i... | 07/18/1995 |
| 5277749 | Methods and apparatus for relieving stress and resisting stencil delamination when performing lift-off processes that utilize high stress metals and/or multiple evaporation steps A layer of photoresist provides a stress relief (or cushion) layer between a lift-off polymer layer and a barrier of multi-level lift-off structures. When multiple evaporation steps are required using the same lift-off pattern, the adhesion between organo... | 01/11/1994 |
