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| Number | Title | Issue Date |
| 7439132 | Semiconductor device comprising capacitor and method of fabricating the same A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. ... | 10/21/2008 |
| 7439579 | Power semiconductor with functional element guide structure A trench transistor is described. In one aspect, the trench transistor has a cell array having a plurality of cell array trenches and a plurality of mesa zones arranged between the cell array trenches, and a semiconductor functional element formed in one of the mesa... | 10/21/2008 |
| 7436009 | Via structures and trench structures and dual damascene structures Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes t... | 10/14/2008 |
| 7436040 | Method and apparatus for diverting void diffusion in integrated circuit conductors A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a di... | 10/14/2008 |
| 7432125 | CMOS image sensor and manufacturing method thereof A CMOS image sensor-manufacturing method includes forming a photodiode on a substrate, forming an insulating layer over the substrate, forming a contact hole in the insulating layer, and forming a gate terminal over the insulating layer. The gate terminal is connect... | 10/07/2008 |
| 7432192 | Post ECP multi-step anneal/Htreatment to reduce film impurity A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a f... | 10/07/2008 |
| 7419863 | Fabrication of semiconductor structure in which complementary field-effect transistors each have hypoabrupt body dopant distribution below at least one source/drain zone Complementary IGFETs (210W and 220W or 530 and 540) are fabricated so that the body dopant concentration in each IGFET decreases by at least 10 in moving from a subsurface location in the body material of that IGFET up to one of it... | 09/02/2008 |
| 7416986 | Test structure and method for detecting via contact shorting in shallow trench isolation regions A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode st... | 08/26/2008 |
| 7416982 | Semiconductor devices and methods for manufacturing the same Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthen... | 08/26/2008 |
| 7413978 | Substrate, electro-optical device, electronic apparatus, method of forming substrate, method of forming electro-optical device, and method of forming electronic apparatus A contact structure, including: a first conductive layer; a insulating layer formed on the first conductive layer; a second conductive layer formed on the insulating layer; and a columnar structure, buried in a direction of film thickness in the insulating layer, el... | 08/19/2008 |
| 7410898 | Methods of fabricating interconnects for semiconductor components In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewall... | 08/12/2008 |
| 7410881 | Method of manufacturing flash memory device A method of manufacturing a flash memory device includes etching an insulating layer provided over a substrate to form a contact hole to define a contact hole exposing a junction region formed on the substrate. The contact hole is filled with a first conductive mate... | 08/12/2008 |
| 7407886 | Method for preparing a contact plug structure A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep tre... | 08/05/2008 |
| 7405461 | Semiconductor device and method for manufacturing semiconductor device A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silico... | 07/29/2008 |
| 7405158 | Methods for depositing tungsten layers employing atomic layer deposition techniques In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process fo... | 07/29/2008 |
| 7400045 | Semiconductor device and method for fabricating the same In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper... | 07/15/2008 |
| 7399706 | Manufacturing method of semiconductor device There is here disclosed a manufacturing method of a semiconductor device, comprising providing a first film by a PVD process in a recess formed in at least one insulating film, the first film containing at least one metal element belonging to any one of the groups | 07/15/2008 |
| 7396751 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes forming a second storage node contact hole with a mask for storage node and securing an overlay margin between a storage node contact hole and a storage node with a hard mask layer that serves as a hard mask... | 07/08/2008 |
| 7396755 | Process and integration scheme for a high sidewall coverage ultra-thin metal seed layer The present invention provides a method of forming a metal seed layer 100. The method includes physical vapor deposition of seed metal 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also ... | 07/08/2008 |
| 7393766 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polys... | 07/01/2008 |
| 7385275 | Shallow trench isolation method for shielding trapped charge in a semiconductor device A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel regi... | 06/10/2008 |
| 7381638 | Fabrication technique using sputter etch and vacuum transfer First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the... | 06/03/2008 |
| 7378341 | Automatic process control of after-etch-inspection critical dimension Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickn... | 05/27/2008 |
| 7365009 | Structure of metal interconnect and fabrication method thereof A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric condu... | 04/29/2008 |
| 7365005 | Method for filling of a recessed structure of a semiconductor device This invention relates to process sequence by high-speed atomic layer chemical vapor processing that includes deposition for diffusion barriers in the etched features on substrate followed by gap fill and subsequent in-situ removal of the blanket films on the top by... | 04/29/2008 |
| 7358180 | Method of forming wiring structure and semiconductor device A micronized wiring structure is obtained by optimizing film forming modes of barrier metal films as being adapted respectively to a via-hole and a wiring groove, wherein sputtering processes are adopted herein, which are specifically the multi-step sputtering proce... | 04/15/2008 |
| 7358172 | Poly filled substrate contact on SOI structure Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next... | 04/15/2008 |
| 7358187 | Coating process for patterned substrate surfaces The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105) which is patterned in a substrate patterning region (102) and has one or more trenche... | 04/15/2008 |
| 7354855 | Semiconductor device and a method of manufacturing the same For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed the... | 04/08/2008 |
| 7348648 | Interconnect structure with a barrier-redundancy feature An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier... | 03/25/2008 |
| 7344975 | Method to reduce charge buildup during high aspect ratio contact etch A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopant... | 03/18/2008 |
| 7341908 | Semiconductor device and method of manufacturing the same Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the ... | 03/11/2008 |
| 7341947 | Methods of forming metal-containing films over surfaces of semiconductor substrates The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least o... | 03/11/2008 |
| 7335589 | Method of forming contact via through multiple layers of dielectric material In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures a... | 02/26/2008 |
| 7327009 | Selective nitride liner formation for shallow trench isolation A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectivel... | 02/05/2008 |
| 7314828 | Repairing method for low-k dielectric materials A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and per... | 01/01/2008 |
| 7312162 | Low temperature plasma deposition process for carbon layer deposition A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone... | 12/25/2007 |
| 7300879 | Methods of fabricating metal wiring in semiconductor devices Manufacturing costs may be reduced and yield may be improved when metal wiring in a semiconductor device is fabricated by a disclosed method including: sequentially forming an etch stop layer, an intermetal insulation layer, an anti-reflection coating layer, and a m... | 11/27/2007 |
| 7300873 | Systems and methods for forming metal-containing layers using vapor deposition processes A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more homoleptic and/or heterole... | 11/27/2007 |
| 7300867 | Dual damascene interconnect structures having different materials for line and via conductors Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those us... | 11/27/2007 |
