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| Number | Title | Issue Date |
| 7443032 | Memory device with chemical vapor deposition of titanium for titanium silicide contacts A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second prec... | 10/28/2008 |
| 7435678 | Method of depositing noble metal electrode using oxidation-reduction reaction Provided is a method of depositing a noble metal layer using an oxidation-reduction reaction. The method includes flowing a noble metal source gas, an oxidizing gas, and a reducing gas into a reaction chamber; and generating plasma in the reaction chamber to form a ... | 10/14/2008 |
| 7435676 | Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is... | 10/14/2008 |
| 7435679 | Alloyed underlayer for microelectronic interconnects Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during... | 10/14/2008 |
| 7432184 | Integrated PVD system using designated PVD chambers A method for making a film stack containing one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes at least one transfer chamber coupled to at least one l... | 10/07/2008 |
| 7432192 | Post ECP multi-step anneal/Htreatment to reduce film impurity A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a f... | 10/07/2008 |
| 7419904 | Method for forming barrier film and method for forming electrode film In the present invention, a barrier film 20 is formed by forming a tungsten nitride film 21 and subsequently by forming a tungsten silicide film 22. The tungsten silicide film 22 is exposed at the surface of the barrier film 20, an... | 09/02/2008 |
| 7420275 | Boron-doped SIC copper diffusion barrier films Copper diffusion barrier films having a boron-doped silicon carbide layer with at least 25% boron by atomic weight of the layer composition have advantages for semiconductor device integration schemes. The films have an integration worthy etch selectivity to carbon ... | 09/02/2008 |
| 7402516 | Method for making integrated circuits Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have... | 07/22/2008 |
| 7396766 | Low-temperature chemical vapor deposition of low-resistivity ruthenium layers A low-temperature chemical vapor deposition process for depositing of a low-resistivity ruthenium metal layers that can be used as barrier/seed layers in Cu metallization schemes. The method includes providing a substrate in a process chamber of a deposition system,... | 07/08/2008 |
| 7394157 | Integrated circuit and seed layers Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the i... | 07/01/2008 |
| 7381638 | Fabrication technique using sputter etch and vacuum transfer First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the... | 06/03/2008 |
| 7378339 | Barrier for use in 3-D integration of circuits A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circ... | 05/27/2008 |
| 7375017 | Method for fabricating semiconductor device having stacked-gate structure A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon... | 05/20/2008 |
| 7368378 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have... | 05/06/2008 |
| 7368377 | Method for selective deposition of a thin self-assembled monolayer A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a... | 05/06/2008 |
| 7365007 | Interconnects with direct metalization and conductive polymer Embodiments include an interconnect or trace of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a via formed on the dielectric layer and to the contact surface. The via sidewalls and perimeter are la... | 04/29/2008 |
| 7361612 | Barrier coating compositions containing silicon and methods of forming photoresist patterns using the same Provided are example embodiments of the invention including a range of polymer structures suitable for incorporation in barrier compositions for use, for example, in immersion photolithography in combination with a suitable solvent or solvent system. These polymers ... | 04/22/2008 |
| 7361613 | Semiconductor device, manufacture and evaluation methods for semiconductor device, and process condition evaluation method A gate insulating film made of silicon oxynitride is disposed on the partial surface area of a semiconductor substrate. A gate electrode is disposed on the gate insulating film. Source and drain regions are disposed on both sides of the gate electrode. An existence ... | 04/22/2008 |
| 7358188 | Method of forming conductive metal silicides by reaction of metal with silicon The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a ni... | 04/15/2008 |
| 7351655 | Copper interconnect systems which use conductive, metal-based cap layers An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 04/01/2008 |
| 7351656 | Semiconductor device having oxidized metal film and manufacture method of the same A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in ... | 04/01/2008 |
| 7348676 | Semiconductor device having a metal wiring structure After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a height substantially smaller than a depth of the contact hole. A metal... | 03/25/2008 |
| 7335590 | Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substr... | 02/26/2008 |
| 7320935 | Semiconductor device using an interconnect The present invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a... | 01/22/2008 |
| 7312162 | Low temperature plasma deposition process for carbon layer deposition A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone... | 12/25/2007 |
| 7312163 | Atomic layer deposition methods, and methods of forming materials over semiconductor substrates The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least... | 12/25/2007 |
| 7301236 | Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dum... | 11/27/2007 |
| 7294570 | Contact integration method A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposi... | 11/13/2007 |
| 7294547 | SONOS memory cell having a graded high-K dielectric A semiconductor memory device may include an intergate dielectric layer of high-K dielectric materials interposed between a charge storing layer and a control gate. The high-K materials may be deposited in such a manner that the materials are gradually graded with r... | 11/13/2007 |
| 7288479 | Method for forming a barrier/seed layer for copper metallization A method for improving adhesion of Cu to a Ru layer in Cu metallization. The method includes providing a substrate in a process chamber of a deposition system, depositing a Ru layer on the substrate in a chemical vapor deposition process, and forming a Cu seed layer... | 10/30/2007 |
| 7279380 | Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method A method of fabricating a chalcogenide memory cell is described. The cross-sectional area of a chalcogenide memory element within the cell is controlled by the thickness of a bottom electrode and the width of a word line. The method allows the formation of ultra sma... | 10/09/2007 |
| 7279408 | Semiconductor device, method for manufacturing the same, and plating solution The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device has an embedded interconnect structure in which an electric conductor, such as copper or silver, is embedded in fine recesses formed in a surfac... | 10/09/2007 |
| 7276434 | Method for filling a contact hole having a small diameter and a large aspect ratio A method for manufacturing a semiconductor device having a semiconductor substrate with a contact hole filled by an aluminum-containing thin film. This manufacturing method includes a step of forming a silicon-containing thin film in a region having a predetermined ... | 10/02/2007 |
| 7274104 | Semiconductor device having an interconnect that increases in impurity concentration as width increases The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of intercon... | 09/25/2007 |
| 7271092 | Boron incorporated diffusion barrier material A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. ... | 09/18/2007 |
| 7262130 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have... | 08/28/2007 |
| 7262505 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on... | 08/28/2007 |
| 7253085 | Deposition methods The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material p... | 08/07/2007 |
| 7253110 | Method and apparatus for forming a barrier metal layer in semiconductor devices A method and apparatus for forming a barrier metal layer in semiconductor devices are disclosed. A disclosed method for forming a barrier metal layer in a semiconductor device forms an interlayer insulating layer on a front face of a semiconductor substrate having a... | 08/07/2007 |
