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| Number | Title | Issue Date |
| 7439125 | Contact structure for a stack DRAM storage capacitor A method for fabricating a contact structure for a stack storage capacitor includes forming the contact structure in a node contact region with contact openings, an insulating liner and a conductive filling material prior to the patterning of bit lines. ... | 10/21/2008 |
| 7427561 | Method for manufacturing semiconductor device A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; fo... | 09/23/2008 |
| 7422982 | Method and apparatus for electroprocessing a substrate with edge profile control A method and apparatus for electroprocessing a substrate is provided. In one embodiment, a method for electroprocessing a substrate includes the steps of biasing a first electrode to establish a first electroprocessing zone between the electrode and the substrate, a... | 09/09/2008 |
| 7417321 | Via structure and process for forming the same Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the ... | 08/26/2008 |
| 7381638 | Fabrication technique using sputter etch and vacuum transfer First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the... | 06/03/2008 |
| 7348676 | Semiconductor device having a metal wiring structure After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a height substantially smaller than a depth of the contact hole. A metal... | 03/25/2008 |
| 7300877 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device that prevents formation of scratches and occurrence of dishing in a CMP process. The method includes forming a first film on a part of a semiconductor substrate, forming a second film all over the semiconductor substr... | 11/27/2007 |
| 7211512 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate. This method includes depositing a thin film seed layer of Palladium (Pd) or Cop... | 05/01/2007 |
| 7208831 | Semiconductor device having multilayer wiring structure and method, wherein connecting portion and wiring layer are formed of same layer A method for manufacturing a semiconductor device includes a step of forming a first groove in a first insulating film, forming a conductive film in the first groove, a step of selectively forming a second insulating film on the conductive film and the first insulat... | 04/24/2007 |
| 7205208 | Method of manufacturing a semiconductor device In a method of manufacturing a semiconductor device, a first trench is formed in a first region of a substrate and a second trench is formed in a second region of the substrate different from the first region. A depth of the first trench is less than that of the sec... | 04/17/2007 |
| 7195700 | Method of electroplating copper layers with flat topography A method of electrochemically filling features on a wafer surface to form a substantially planar copper layer is provided. The features to be filled includes a first feature that is an unfilled feature with the smallest width and a second feature having the next lar... | 03/27/2007 |
| 7186574 | CMP process metrology test structures A method for forming metrology structures for a CMP process is described. A trench edge is formed in a base material or stack of materials which are preferably deposited as part of the process of fabricating the production structures on the wafer. A covering film of... | 03/06/2007 |
| 7163894 | Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier... | 01/16/2007 |
| 7138340 | Method for fabricating semiconductor device without damaging hard mask during contact formation process Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer... | 11/21/2006 |
| 7105925 | Differential planarization Method and structure for optimizing and controlling chemical mechanical planarization are disclosed. Embodiments of the invention include planarization techniques to make nonplanar surfaces comprising alternating metal and intermetal layers. Relative protrusion dime... | 09/12/2006 |
| 6703324 | Mechanically reinforced highly porous low dielectric constant films A porous medium, such as a low dielectric constant film, can be made into an aggregate material to provide increased mechanical strength on a temporary basis. This can be achieved by, for example, a permeable modification treatment of the porous medium. B... | 03/09/2004 |
| 6699785 | Conductor abrasiveless chemical-mechanical polishing in integrated circuit interconnects A manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A... | 03/02/2004 |
| 6696759 | Semiconductor device with diamond-like carbon layer as a polish-stop layer A semiconductor structure includes a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate in a damascene process flow. The semiconductor structure includes a substrate having a dielectric layer f... | 02/24/2004 |
| 6696761 | Method to encapsulate copper plug for interconnect metallization An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is part... | 02/24/2004 |
| 6696358 | Viscous protective overlayers for planarization of integrated circuits The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The pres... | 02/24/2004 |
| 6693036 | Method for producing semiconductor device polishing apparatus, and polishing method A method for producing a semiconductor device, polishing method, and polishing apparatus, suppressing occurrence of dishing and erosion in a flattening process by polishing of a metal film for constituting an interconnection of a semiconductor device havi... | 02/17/2004 |
| 6689693 | Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as... | 02/10/2004 |
| 6683006 | Film forming method and film forming apparatus After coating a resist for silylation on the semi-conductor substrate, the resist is exposed with a pattern. Then the silylation process is performed to form a silylated layer and the silylated layer is hardened with performing an electron beam processing... | 01/27/2004 |
| 6680500 | Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers A semiconductor device (100) and method of fabrication thereof, wherein a plurality of first conductive lines (116) are formed in a dielectric layer (112) over a substrate (110), and an insulating cap layer (140) is disposed over the first conductive line... | 01/20/2004 |
| 6667147 | Electronic device manufacture Disclosed are methods of manufacturing electronic devices, particularly integrated circuits. Such methods include the use of low dielectric constant material prepared by using a removable porogen material.... | 12/23/2003 |
| 6660638 | CMP process leaving no residual oxide layer or slurry particles Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effec... | 12/09/2003 |
| 6660650 | Selective aluminum plug formation and etchback process An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate having an interconnecting structure comprised of aluminum, the method comprising the steps of: forming a conductive structure (layers 120... | 12/09/2003 |
| 6660629 | Chemical mechanical polishing method for fabricating copper damascene structure A method of fabricating a copper damascene. The method is applicable to a substrate, which substrate has a dielectric layer formed thereon. The method comprising forming a damascene opening in the dielectric layer, forming a barrier layer which conforms t... | 12/09/2003 |
| 6660627 | Method for planarization of wafers with high selectivities A method for planarization of a semiconductor wafer with a high selectivity is describe. The semiconductor wafer has a hard mask, a stop layer disposed on the hard mask, and a barrier layer disposed on the stop layer. The method includes performing a chem... | 12/09/2003 |
| 6653226 | Method for electrochemical planarization of metal surfaces Methods and apparatus are used for electrochemical planarization of an electrically conductive material surface with varying topography from a partially fabricated integrated circuit, in which protruding regions of the conductive material are removed more... | 11/25/2003 |
| 6653233 | Process of providing a semiconductor device with electrical interconnection capability A process of providing a semiconductor device with electrical interconnection capability wherein a sacrificial material is introduced into topographical features of the semiconductor device prior to chemical mechanical polishing so that debris formed duri... | 11/25/2003 |
| 6653224 | Methods for fabricating interconnect structures having Low K dielectric properties Methods for fabricating semiconductor structures having LowK dielectric properties are provided. In one example, a copper dual damascene structure is fabricated in a LowK dielectric insulator including forming a capping film over the insulator before feat... | 11/25/2003 |
| 6649523 | Method and system to provide material removal and planarization employing a reactive pad Systems and methods to remove a first material located on a top surface of a workpiece are presented according to one aspect of the present invention. According to an exemplary method, the pad including a second material is positioned proximate to the wor... | 11/18/2003 |
| 6649513 | Copper back-end-of-line by electropolish A method of fabricating a planarized metal structure comprising the following steps. A structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least ... | 11/18/2003 |
| 6645863 | Method of manufacturing semiconductor device and semiconductor device The invention provides a method of manufacturing a semiconductor device which can reduce or prevent abrasive material from remaining in an indentation in a surface after a CMP process. After forming a titanium nitride film (5), a tungsten film (6) is formed on... | 11/11/2003 |
| 6645869 | Etching back process to improve topographic planarization of a polysilicon layer An etching back process to improve topographic planarization of a polysilicon layer. First, a polysilicon layer is formed to fill a contact hole between two adjacent insulating structures and cover the entire surface of a semiconductor substrate to a pred... | 11/11/2003 |
| 6638863 | Electropolishing metal layers on wafers having trenches or vias with dummy structures In electropolishing a metal layer on a semiconductor wafer, a dielectric layer is formed on the semiconductor wafer. The dielectric layer is formed with a recessed area and a non-recessed area. A plurality of dummy structures are formed within the recesse... | 10/28/2003 |
| 6639288 | Semiconductor device with a particular conductor arrangement A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high a... | 10/28/2003 |
| 6638775 | Method for fabricating semiconductor memory device The present invention provides a method including the steps of: forming a first diffusion barrier on an insulating layer and in a contact hole; forming a conductive layer on the first diffusion barrier; forming a conductive plug in the contact hole by rem... | 10/28/2003 |
| 6638868 | Method for preventing or reducing anodic Cu corrosion during CMP A method and apparatus for implementing the method for preventing or reducing corrosion of copper containing features included in a semiconductor wafer in a chemical mechanical polishing (CMP) process the method providing at least one semiconductor wafer ... | 10/28/2003 |
