Bizarre Patents
A method for inducing cats to exercise consists of directing a beam of invisible light produced by a hand-held laser apparatus onto the floor or wall.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7442567 | Method for fabricating transflective liquid crystal display An exemplary method for fabricating a transflective liquid crystal display is provided. The transflective liquid crystal display includes a substrate (200) having a transmission region (201) and a reflection region (202). The method includes: fo... | 10/28/2008 |
| 7429530 | Method of forming a pattern, method of forming wiring, semiconductor device, TFT device, electro-optic device, and electronic instrument A method of forming a pattern of a functional layer on a surface of a substrate, where a pattern region, to which the pattern is provided, is edged with a boundary layer, and has a first region and a second region communicated with the first region and having a narr... | 09/30/2008 |
| 7427561 | Method for manufacturing semiconductor device A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; fo... | 09/23/2008 |
| 7413985 | Method for forming a self-aligned nitrogen-containing copper silicide capping layer in a microstructure device By forming a copper/silicon/nitrogen alloy in a surface portion of a copper-containing region on the basis of a precursor layer, highly controllable and reliable process conditions may be established. The precursor layer may be formed on the basis of a liquid precur... | 08/19/2008 |
| 7413981 | Pitch doubled circuit layout In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry includes providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other... | 08/19/2008 |
| 7405111 | Methods for manufacturing an active matrix display device The present invention is to carry out stable doping and to prevent the drastic pressure change in a treatment chamber by reducing degasification of resist during adding impurities. In the present invention, the stability of the impurity ion injection can be ensured ... | 07/29/2008 |
| 7399359 | Method and system for providing a thin film with a controlled crystal orientation using pulsed laser induced melting and nucleation-initiated crystallization Method and system for generating a metal thin film with a uniform crystalline orientation and a controlled crystalline microstructure are provided. For example, a metal layer is irradicated with a pulsed laser to completely melt the film throughout its entire thickn... | 07/15/2008 |
| 7396765 | Method of fabricating a liquid crystal display device A method of fabricating a liquid crystal display device according to an embodiment of the present invention includes forming first and second conductive layers on a substrate, wherein the first layer is transparent; patterning the second conductive layer and the fir... | 07/08/2008 |
| 7396774 | Methods for forming an enriched metal oxide surface Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state are provided. A metal oxide surface that is enriched with metal oxide in its higher oxidation state is also provided. ... | 07/08/2008 |
| 7387971 | Fabricating method for flat panel display device A fabricating method for a flat panel display device having a thin film pattern over a substrate is disclosed. The fabricating method includes depositing a hydrophilic resin over a substrate and patterning the hydrophilic resin to form hydrophilic resin patterns ove... | 06/17/2008 |
| 7361586 | Preamorphization to minimize void formation Methods are described for eliminating void formation during the fabrication of and/or operation of memory cells/devices. According to one aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, f... | 04/22/2008 |
| 7358169 | Laser-assisted deposition A method is provided for depositing a patterning material onto an optically transparent substrate by the use of a laser beam. A solid layer of a patterning material is placed adjacent to a receiving surface of the substrate. A laser beam is directed at an incident a... | 04/15/2008 |
| 7344979 | High pressure treatment for improved grain growth and void reduction A copper film is annealed at high pressure to enhance grain growth and remove voids. Other films, such as dielectrics, may also be suitable. High pressure can be used in conjunction with temperatures lower than room temperature for annealing or higher temperatures m... | 03/18/2008 |
| 7341947 | Methods of forming metal-containing films over surfaces of semiconductor substrates The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least o... | 03/11/2008 |
| 7316934 | Personalized hardware A system for personalizing one or more electrical circuits having plurality of layers with electrical characteristics. The layers being produced by an electrical characteristic determination process (ECDP). The system for personalizing includes a wafer stage for rec... | 01/08/2008 |
| 7307022 | Method of treating conductive layer for use in a circuitized substrate and method of making said substrate having said conductive layer as part thereof A method of treating a conductive layer to assure enhanced adhesion of the layer to selected dielectric layers used to form a circuitized substrate. The conductive layer includes at least one surface with the appropriate roughness to enable such adhesion and also go... | 12/11/2007 |
| 7300833 | Process for producing semiconductor integrated circuit device When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and c... | 11/27/2007 |
| 7274078 | Devices having vertically-disposed nanofabric articles and methods of making the same Electro-mechanical switches and memory cells using vertically-disposed nanofabric articles and methods of making the same are described. An electro-mechanical device, includes a structure having a major horizontal surface and a channel formed therein. A conductive t... | 09/25/2007 |
| 7262500 | Interconnection structure In a metal film production apparatus, a copper plate member is etched with a Cl2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl2 gas; and the temperatures of the copper plate member and a substrate and a diff... | 08/28/2007 |
| 7259083 | Local interconnect manufacturing process The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The fi... | 08/21/2007 |
| 7256141 | Interface layer between dual polycrystalline silicon layers A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer o... | 08/14/2007 |
| 7211512 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate. This method includes depositing a thin film seed layer of Palladium (Pd) or Cop... | 05/01/2007 |
| 7208411 | Method of depositing metal film and metal deposition cluster tool including supercritical drying/cleaning module A method of depositing a metal film on a substrate includes a supercritical preclean step, a supercritical desorb step, and a metal deposition step. Preferably, the preclean step comprises maintaining supercritical carbon dioxide and a chelating agent in contact wit... | 04/24/2007 |
| 7166543 | Methods for forming an enriched metal oxide surface for use in a semiconductor device Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state for use in a semiconductor device are provided. A metal oxide surface that is enriched with metal oxide in its higher oxidation state for use in a semiconductor ... | 01/23/2007 |
| 7125742 | Multi-passivation layer structure for organic thin-film transistors and method for fabricating the same The present invention discloses a multi-passivation layer structure for organic thin-film transistors and a method for fabricating the same by spin coating, inject printing, screen printing and micro-contact on organic thin-film transistors. The multi-passivation la... | 10/24/2006 |
| 7105375 | Reverse printing A method of patterning organic semiconductor layers of electronic devices utilizing reverse printing. ... | 09/12/2006 |
| 7087523 | Method for producing a structure using nanoparticles For forming a fine structure of a desired material, nanoparticles of the same material are prepared in a suspension. A layer of the suspension is applied by a drop-on-demand printing system to a substrate. At least part of the layer is exposed to laser light for mel... | 08/08/2006 |
| 6794270 | Method for shallow trench isolation fabrication and partial oxide layer removal A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench b... | 09/21/2004 |
| 6723631 | Fabrication method of semiconductor integrated circuit device The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out i... | 04/20/2004 |
| 6703309 | Method of reducing oxidation of metal structures using ion implantation, and device formed by such method The present invention is generally directed to a method of reducing oxidation of metal structures using ion implantation, and a device constructed in accordance with the method. In one illustrative embodiment, the method comprises providing a semiconducti... | 03/09/2004 |
| 6703710 | Dual damascene metal trace with reduced RF impedance resulting from the skin effect The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor ... | 03/09/2004 |
| 6703301 | Method of preventing tungsten plugs from corrosion Tungsten plugs are prevented from corrosion, during fabrication of semiconductor devices, where the tungsten plug is formed in a substrate and coupled with a wire formed on the substrate. The substrate is dipped into a non-ionic benign solvent which subst... | 03/09/2004 |
| 6699777 | Etch stop layer in poly-metal structures In accordance with one embodiment of the present invention, a method of interfacing a poly-metal stack and a semiconductor substrate is provided where an etch stop layer is provided in a polysilicon region of the stack. The present invention also addresse... | 03/02/2004 |
| 6699786 | Method for forming a semiconductor device that uses a low resistance tungsten silicide layer with a strong adherence to an underlayer Tungsten silicide WSix is grown through reduction of WF6 with SiCl2 H2, and the flow rate between WF6 and SiCl2 H2 is controlled in such a manner that the composition ratio x ranges ... | 03/02/2004 |
| 6696357 | Method for manufacturing semiconductor integrated circuit devices using a conductive layer to prevent peeling between a bonding pad and an underlying insulating film Peeling between a bonding pad and an insulating film which underlies the bonding pad is to be prevented. A laminate film constituted mainly by W which is higher in mechanical strength than a wiring layer using an Al alloy film as a main conductive layer a... | 02/24/2004 |
| 6692580 | Method of cleaning a dual damascene structure A method of cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer, exposing the first metal la... | 02/17/2004 |
| 6693040 | Method for cleaning the contact area of a metal line A method for cleaning a contact area of a metal line wherein a nitride barrier layer is formed on a sidewall of an insulating interlayer within the contact area by introducing the nitrogen-based radical to the contact area, whereby it is possible to preve... | 02/17/2004 |
| 6693334 | Semiconductor integrated circuit device A shield portion 5 has such a multi-layer wiring construction comprised of three wiring layers as to correspond to a macro cell and also via contacts formed with a predetermined spacing therebetween and is supplied with a predetermined potential (for exam... | 02/17/2004 |
| 6693030 | Reactive preclean prior to metallization for sub-quarter micron application The present invention generally provides a precleaning process prior to moralization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF | 02/17/2004 |
| 6690580 | Integrated circuit structure with dielectric islands in metallized regions This disclosure describes use of dielectric islands embedded in metallized regions of a semiconductor device. The islands are formed in a cavity of a dielectric layer, as upright pillars attached at their base to an underlying dielectric. The islands brea... | 02/10/2004 |
