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| Number | Title | Issue Date |
| 7439172 | Circuit structure with low dielectric constant regions and method of forming same A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a pluralit... | 10/21/2008 |
| 7425501 | Semiconductor structure implementing sacrificial material and methods for making and implementing the same A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is pe... | 09/16/2008 |
| 7422975 | Composite inter-level dielectric structure for an integrated circuit A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Nex... | 09/09/2008 |
| 7422940 | Layer arrangement A process for producing a layer arrangement, in which a plurality of electrically conductive structures are formed on a substrate, a first electrically insulating layer is formed on the plurality of electrically conductive structures, in such a manner than trenches ... | 09/09/2008 |
| 7385276 | Semiconductor device, and method for manufacturing the same The invention is characterized by attaining a lower dielectric constant and including an inorganic dielectric film which is formed on the surface of a substrate and has a cyclic porous structure having a pore ratio of 50% or higher. ... | 06/10/2008 |
| 7371677 | Laterally grown nanotubes and method of formation A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portio... | 05/13/2008 |
| 7361991 | Closed air gap interconnect structure A closed air gap interconnect structure is described. The structure includes discrete regions of a permanent support dielectric under the interconnect lines so that the lines are substantially surrounded by air except for the discrete regions of the support dielectr... | 04/22/2008 |
| 7352019 | Capacitance reduction by tunnel formation for use with a semiconductor device A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectr... | 04/01/2008 |
| 7348281 | Method of filling structures for forming via-first dual damascene interconnects A method of forming via-first, dual damascene interconnect structures by using a gap-filling, bottom anti-reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating ... | 03/25/2008 |
| 7332406 | Air gap interconnect structure and method A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from th... | 02/19/2008 |
| 7319274 | Methods for selective integration of airgaps and devices made by such methods Methods for the production of airgaps in semiconductor devices and devices produced using such methods are disclosed. An example semiconductor device includes a damascene stack formed using such methods. The damascene stack includes a patterned dielectric layer incl... | 01/15/2008 |
| 7316934 | Personalized hardware A system for personalizing one or more electrical circuits having plurality of layers with electrical characteristics. The layers being produced by an electrical characteristic determination process (ECDP). The system for personalizing includes a wafer stage for rec... | 01/08/2008 |
| 7316957 | Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are provided. A gate insulating film is formed under a vacuum condition to prevent deterioration of reliability of the device due to degradation of a gate insulating material and to have stable operating... | 01/08/2008 |
| 7309649 | Method of forming closed air gap interconnects and structures formed thereby A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remai... | 12/18/2007 |
| 7211496 | Freestanding multiplayer IC wiring structure A dielectric wiring structure and method of manufacture therefor. The wiring structure includes air dielectric formed in a hemisphere. The wiring structure also includes, in embodiments, a method of simultaneously forming a MEMS structure with a transistor circuit u... | 05/01/2007 |
| 7190046 | Bipolar transistor having reduced collector-base capacitance Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at lea... | 03/13/2007 |
| 7157387 | Techniques to create low K ILD for BEOL One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at l... | 01/02/2007 |
| 7105420 | Method to fabricate horizontal air columns underneath metal inductor A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing... | 09/12/2006 |
| 6703314 | Method for fabricating semiconductor device Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive p... | 03/09/2004 |
| 6696315 | Semiconductor device configuration with cavities of submicrometer dimensions and method of fabricating structured cavities Cavities of submicron dimension are in a cavity layer of a semiconductor device. For that purpose, processing material is deposited on ridges of a working layer that is structured from ridges and trenches. The processing material is polymerized and the po... | 02/24/2004 |
| 6693355 | Method of manufacturing a semiconductor device with an air gap formed using a photosensitive material A semiconductor structure (10) has one or more air gaps (44, 46) formed on a same layer with an interlevel dielectric (ILD) (30) using a common dielectric material (16) that is photosensitive. Additional ILDs (124, 162) may be formed on the layer. The pho... | 02/17/2004 |
| 6693335 | Semiconductor raised source-drain structure A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the d... | 02/17/2004 |
| 6686643 | Substrate with at least two metal structures deposited thereon, and method for fabricating the same Metal structures that can be produced by a damascene process are disposed in a first insulating layer and a second insulating layer is disposed above the latter. There is in each case at least one cavity which is disposed between the metal structures, is ... | 02/03/2004 |
| 6686636 | Semiconductor raised source-drain structure A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication wi... | 02/03/2004 |
| 6683355 | Semiconductor raised source-drain structure A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication wi... | 01/27/2004 |
| 6682999 | Semiconductor device having multilevel interconnections and method of manufacture thereof The present invention provides, in one aspect, a method for fabricating an interconnect system within a semiconductor device. In this particular embodiment, the method comprises forming a conductive layer over a substrate of the semiconductor device, such... | 01/27/2004 |
| 6677682 | Multilayer interconnection structure including an alignment mark An interlayer insulating film (21) is formed on a substrate (1), and a polysilicon layer (10) is formed on the interlayer insulating film (21). An interlayer insulating film (22) is formed to cover the polysilicon layer (10), and a polysilicon layer (11) ... | 01/13/2004 |
| 6670719 | Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the... | 12/30/2003 |
| 6670022 | Nanoporous dielectric films with graded density and process for making such films The present invention relates to nanoporous dielectric films and to a process for their manufacture. A substrate having a plurality of raised lines on its surface is provided with a relatively high porosity, low dielectric constant, silicon containing pol... | 12/30/2003 |
| 6667147 | Electronic device manufacture Disclosed are methods of manufacturing electronic devices, particularly integrated circuits. Such methods include the use of low dielectric constant material prepared by using a removable porogen material.... | 12/23/2003 |
| 6667552 | Low dielectric metal silicide lined interconnection system Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and depositing a metal silicide to line the interconnection sy... | 12/23/2003 |
| 6661094 | Semiconductor device having a dual damascene interconnect spaced from a support structure A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive... | 12/09/2003 |
| 6660546 | Method of etching an object, method of repairing pattern, nitride pattern and semiconductor device A method of manufacturing a compound layer, containing a nitrified metal as a mayor component thereof and having a predetermined microstructure pattern, includes: an ion implantation step for implanting hydrogen ions into a predetermined region of a compo... | 12/09/2003 |
| 6656822 | Method for reduced capacitance interconnect system using gaseous implants into the ILD A method of decreasing the dielectric constant of a dielectric layer. First, a dielectric layer is formed on a first conductive layer. A substance is then implanted into the dielectric layer.... | 12/02/2003 |
| 6645873 | Method for manufacturing a semiconductor device A method of processing a semiconductor substrate involves etching a SiOF layer with HF or HF+H2 O. The method can be used to form hollow structures in semiconductor substrates and thus provides a way to make interlayer insulators.... | 11/11/2003 |
| 6645850 | Semiconductor device having cavities with submicrometer dimensions generated by a swelling process A method creates structured cavities with submicrometer dimensions in a cavity layer of a semiconductor device. A processing material that incorporates a swelling agent is deposited on ridges of a working layer that is constructed of ridges and trenches. ... | 11/11/2003 |
| 6642138 | Process of making dual damascene structures using a sacrificial polymer A method is provided to deposit and pattern a sacrificial polymer, and form metal layers. A double hard mask is used to pattern and etch the sacrificial polymer. The double hard mask may be formed at temperatures below 400° C. The sacrificial polymer is ... | 11/04/2003 |
| 6635967 | Air gap semiconductor structure and method of manufacture An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first... | 10/21/2003 |
| 6633074 | Integrated circuit wiring with low RC time delay The present invention is directed to a semiconductor interconnect structure comprised of a promoter layer defining openings and a metal layer having a portion elevated above the substrate assembly and a portion that fills the openings. The metal layer is ... | 10/14/2003 |
| 6627549 | Methods for making nearly planar dielectric films in integrated circuits In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric l... | 09/30/2003 |
