Class 257/E21.58 - Planarizing dielectric (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.576. This subclass
No. of patents: 455
Last issue date: 09/02/2008

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Number	Title	Issue Date
7419909	Methods of forming a semiconductor device that allow patterns in different regions that have different pitches to be connected Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with...	09/02/2008
7338905	Semiconductor device manufacture method An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench. Chemical mechanical polishing is executed to expose the insulating sur...	03/04/2008
7253392	Image sensor with photo diode gate A photodiode has a photodiode gate structure on the surface of the substrate. The photodiode may be located in a pixel sensor cell comprising a substrate having a first surface level. The photodiode has a first doped region of a first conductivity type and a second ...	08/07/2007
7163881	Method for forming CMOS structure with void-free dielectric film A process for forming a void-free dielectric layer is disclosed in which adjoining gate film stacks are formed on a semiconductor substrate. Each gate film stack includes a silicide layer and a hard mask that overlies the silicide layer. A first selective etch is pe...	01/16/2007
7151023	Metal gate MOSFET by full semiconductor metal alloy conversion A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to parti...	12/19/2006
7105925	Differential planarization Method and structure for optimizing and controlling chemical mechanical planarization are disclosed. Embodiments of the invention include planarization techniques to make nonplanar surfaces comprising alternating metal and intermetal layers. Relative protrusion dime...	09/12/2006
7105452	Method of planarizing a semiconductor substrate with an etching chemistry The present invention provides a method of planarizing a substrate, the method including, forming, on the substrate, a patterned layer having a first shape associated therewith; and processing the patterned layer, with the first shape compensating for variations in ...	09/12/2006
6703321	Low thermal budget solution for PMD application using sacvd layer The present invention provides exemplary methods, apparatus and systems for planarizing an insulating layer, such as a borophosphosilicate glass (BPSG) layer, deposited over a substrate. In one embodiment, a substrate (140) is inserted into a substrate pr...	03/09/2004
6696359	Design layout method for metal lines of an integrated circuit A process to enhance metal line layout designs is provided and includes two separate control spaces to address capacitive issues along speed sensitive pathways in an integrated circuit structure without negatively impacting the Werner Fill process. One co...	02/24/2004
6683382	Semiconductor device having an interconnect layer with a plurality of layout regions having substantially uniform densities of active interconnects and dummy fills A semiconductor device with an interconnect layer having a plurality of layout regions of active interconnects and dummy fills for uniform planarization. In one embodiment, the device will have at least one interconnect layer with a plurality of layout re...	01/27/2004
6677682	Multilayer interconnection structure including an alignment mark An interlayer insulating film (21) is formed on a substrate (1), and a polysilicon layer (10) is formed on the interlayer insulating film (21). An interlayer insulating film (22) is formed to cover the polysilicon layer (10), and a polysilicon layer (11) ...	01/13/2004
6667531	Method and apparatus for a deposited fill layer A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed w...	12/23/2003
6664642	Semiconductor integrated circuit device Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnecti...	12/16/2003
6664189	Removal of wafer edge defocus due to CMP At the conclusion of chemical mechanical polishing (CMP) there is found to be a topography difference at the periphery of the wafer. For example, for a 200 mm wafer, the oxide surface in a peripheral region up to 20 mm wide, may end up about 1,000 Å abov...	12/16/2003
6660618	Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems Excessive variation in vertical (i.e., inter-level) capacitance of multi-level metallization semiconductor devices resulting in racing of clock skew circuitry of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, ...	12/09/2003
6656814	Methods of fabricating integrated circuit devices including distributed and isolated dummy conductive regions An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines ...	12/02/2003
6656794	Method of manufacturing semiconductor device including a memory area and a logic circuit area The manufacturing method of the invention performs over etching to remove an upper portion of a conductive layer in a logic circuit area of a semiconductor device, simultaneously with etching out a stopper layer. The method subsequently patterns the condu...	12/02/2003
6653224	Methods for fabricating interconnect structures having Low K dielectric properties Methods for fabricating semiconductor structures having LowK dielectric properties are provided. In one example, a copper dual damascene structure is fabricated in a LowK dielectric insulator including forming a capping film over the insulator before feat...	11/25/2003
6653717	Enhancement in throughput and planarity during CMP using a dielectric stack containing an HDP oxide A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 ...	11/25/2003
6649451	Structure and method for wafer comprising dielectric and semiconductor Wafers of the present invention comprise a semiconductor layer and a dielectric layer. The semiconductor layer is patterned to form semiconductor regions, and the dielectric layer is deposited on top of the semiconductor layer. Chemical mechanical planari...	11/18/2003
6642114	Semiconductor device and method for fabricating the same A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insula...	11/04/2003
6642147	Method of making thermally stable planarizing films Disclosed is a method of protecting semiconductor areas while exposing a structures for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma film of a silicon compound, selected from the group silicon o...	11/04/2003
6635943	Method and system for reducing charge gain and charge loss in interlayer dielectric formation A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capa...	10/21/2003
6632716	Semiconductor device and manufacturing method thereof A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a g...	10/14/2003
6630390	Method of forming a semiconductor device using a carbon doped oxide layer to control the chemical mechanical polishing of a dielectric layer A method for making a semiconductor device is described. That method comprises forming a carbon doped oxide containing layer and a dielectric layer on a substrate, such that at least part of the dielectric layer is located above at least part of the carbo...	10/07/2003
6627551	Method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process This invention discloses a method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process. There is step height difference on surface of the interlevel dielectric layer between the memory array and the logic device, ...	09/30/2003
6627549	Methods for making nearly planar dielectric films in integrated circuits In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric l...	09/30/2003
6624076	Semiconductor device and method for fabricating the same First, a pattern of electrodes or interconnects is formed on a semiconductor substrate. Next, a first insulating film, which will be dry-etched at a relatively high rate and exhibit relatively high planarity, is deposited over the substrate as well as ove...	09/23/2003
6624091	Methods of forming gap fill and layers formed thereby A method of forming a fill layer over a layer in a semiconductor stack having gaps of high aspect ratio topography, and products produced thereby....	09/23/2003
6621117	Semiconductor device having memory cell and peripheral circuitry with dummy electrode A semiconductor device includes: a semiconductor substrate having a memory cell section and a peripheral circuit section defined in a plane; a floating gate electrode formed on semiconductor substrate in the memory cell section; a control gate electrode l...	09/16/2003
6617241	Method of thick film planarization Planarization of the top surfaces of layers that are more than about a micron thick is beset with problems not encountered in thinner layers. These problems have been overcome by means of a process that, initially allows the formation of `horns` in the su...	09/09/2003
6613623	High fMAX deep submicron MOSFET A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A f...	09/02/2003
6610573	Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate A memory cell comprises a region containing one or more vertical pass transistor, and a support region containing, e.g. one or more planar transistors. During processing, a polysilicon layer is formed for the planar devices gate. The polysilicon layer is ...	08/26/2003
6611060	Semiconductor device having a damascene type wiring layer A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (=removal rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation...	08/26/2003
6608335	Grounded fill in a large scale integrated circuit An integrated circuit has a plurality of metal layers separated by a plurality of insulating layers. The integrated circuit comprises a pair of conductors on a first metal layer; at least one conductive fill element disposed between the conductors; and a ...	08/19/2003
6579785	Method of making multi-level wiring in a semiconductor device A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate lay...	06/17/2003
6576514	Method of forming a three-dimensional polysilicon layer on a semiconductor wafer A semiconductor wafer includes a substrate, a polysilicon layer, and a sacrificial layer on the polysilicon layer. A dielectric layer is formed to cover the substrate and the sacrificial layer. A portion of the dielectric layer is removed to expose an upp...	06/10/2003
6567964	Continuously variable dummy pattern density generating systems, methods and computer program products for patterning integrated circuits Dummy patterns are generated for a region of an integrated circuit that is divided into buckets by obtaining a local pattern density for a respective bucket and adjusting a density of the dummy pattern for the respective bucket as a continuously variable ...	05/20/2003
6566242	Dual damascene copper interconnect to a damascene tungsten wiring level A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silic...	05/20/2003
6555466	Two-step chemical-mechanical planarization for damascene structures on semiconductor wafers A method of improving planarity of semiconductor wafer surfaces containing damascene and dual-damascene circuitry using chemical-mechanical polishing techniques. The method includes using a first polishing step to substantially remove excess surface metal...	04/29/2003

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Class 257/E21.58 - Planarizing dielectric (EPO)