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| Number | Title | Issue Date |
| 7439171 | Method for manufacturing electronic device A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and the via hole and the trench for the interconnect are plugged with an electric co... | 10/21/2008 |
| 7439185 | Method for fabricating semiconductor device and semiconductor device A method of fabricating a semiconductor device having an air-gapped multilayer interconnect wiring structure is disclosed. After having formed a first thin film on or above a substrate, define a first opening in the first thin film. Then, deposit a conductive materi... | 10/21/2008 |
| 7435679 | Alloyed underlayer for microelectronic interconnects Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during... | 10/14/2008 |
| 7435686 | Semiconductor processing using energized hydrogen gas and in combination with wet cleaning A method of fabricating a semiconductor device. The method comprises subjecting a substrate having formed thereon photoresist layer to a plasma hydrogen, the substrate further having formed thereon a sacrificial layer; contacting the photoresist layer with a photore... | 10/14/2008 |
| 7435685 | Method of forming a low-K dual damascene interconnect structure A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is the... | 10/14/2008 |
| 7432191 | Method of forming a dual damascene structure utilizing a developable anti-reflective coating A method of patterning a structure in a thin film on a substrate is described. A film stack on the substrate includes the thin film on the substrate, a developable anti-reflective coating (ARC) layer on the thin film, and a first photo-resist layer on the developabl... | 10/07/2008 |
| 7425502 | Minimizing resist poisoning in the manufacture of semiconductor devices The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substr... | 09/16/2008 |
| 7422981 | Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole A method for manufacturing a semiconductor device is provided, in which the lengths of a wiring trench and a via hole in a depth direction are easily controlled. A component having a first insulating film is prepared on a substrate, and a layer is disposed on the ab... | 09/09/2008 |
| 7419847 | Method for forming metal interconnection of semiconductor device A method for forming a metal interconnection of a semiconductor device avoids over-etching and under-etching through the use of the “self-stop” function of a nitridation layer, to prevent the occurrence of openings and voids in a copper interconnection and to ob... | 09/02/2008 |
| 7416992 | Method of patterning a low-k dielectric using a hard mask By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes. ... | 08/26/2008 |
| 7416973 | Method of increasing the etch selectivity in a contact structure of semiconductor devices By providing an additional silicon dioxide based etch stop layer, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. In another aspect, the etch selectiv... | 08/26/2008 |
| 7410895 | Methods for forming interconnect structures A method for forming an interconnect structure. A substrate is provided with a low-k dielectric layer thereon. At least one conductive feature is then formed in the low-k dielectric layer. A cap layer is formed overlying the low-k dielectric layer, and the conductiv... | 08/12/2008 |
| 7405153 | Method for direct electroplating of copper onto a non-copper plateable layer A process for the formation of an interconnect in a semiconductor structure including the steps of forming a dielectric layer on a substrate, forming a first barrier layer on the dielectric layer, forming a second barrier layer on the first barrier layer, wherein th... | 07/29/2008 |
| 7402514 | Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the step... | 07/22/2008 |
| 7399700 | Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patt... | 07/15/2008 |
| 7396761 | Semiconductor device and method of manufacturing the same In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewa... | 07/08/2008 |
| 7387961 | Dual damascene with via liner A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in t... | 06/17/2008 |
| 7378350 | Formation of low resistance via contacts in interconnect structures A method of fabricating BEOL interconnect structures on a semiconductor device having a plurality of via contacts with low via contact resistance is provided. The method includes the steps of: a) forming a porous or dense low k dielectric layer on a substrate; b) fo... | 05/27/2008 |
| 7378343 | Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-ba... | 05/27/2008 |
| 7375004 | Method of making an isolation trench and resulting isolation trench A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of t... | 05/20/2008 |
| 7375028 | Method for manufacturing a semiconductor device A semiconductor device may be manufactured by a method that includes forming an etch stop layer on a semiconductor substrate, sequentially forming a first interlayer insulating layer, a first diffusion barrier, a second interlayer insulating layer, and a second diff... | 05/20/2008 |
| 7375030 | Method to assay sacrificial light absorbing materials and spin on glass materials for chemical origin of defectivity Numerous embodiments of a method to assay sacrificial material are disclosed. In one embodiment, a sacrificial material may be analyzed by high performance liquid chromatography. Chemical markers that correlate with material contaminants in the sacrificial material ... | 05/20/2008 |
| 7372154 | Semiconductor device As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked ... | 05/13/2008 |
| 7372156 | Method to fabricate aligned dual damascene openings An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patt... | 05/13/2008 |
| 7361589 | Copper interconnect systems which use conductive, metal-based cap layers An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 04/22/2008 |
| 7361992 | Semiconductor device including interconnects formed by damascene process and manufacturing method thereof After etching the interlayer dielectric film 4 formed on the lower layer interconnect line 1 into a shape with holes, the upper layer dielectric film 6 is etched into a shape with trenches utilizing the etching stopper 5. The etching stop... | 04/22/2008 |
| 7358182 | Method of forming an interconnect structure A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the... | 04/15/2008 |
| 7354859 | Method of manufacturing semiconductor device In a dual damascene process to form a fine interconnection structure, a semiconductor manufacturing method includes: forming a first film to be etched on an insulating layer on a semiconductor substrate; forming a first mask film with an opening on the first film; f... | 04/08/2008 |
| 7354856 | Method for forming dual damascene structures with tapered via portions and improved performance The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer... | 04/08/2008 |
| 7351635 | Method of fabricating microelectronic device using super critical fluid Methods of fabricating a microelectronic device having improved performance characteristics are disclosed which are characterized by using super critical fluid to perform a material removal step. In one illustrative embodiment, the method includes preparing a substr... | 04/01/2008 |
| 7352064 | Multiple layer resist scheme implementing etch recipe particular to each layer Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first plan... | 04/01/2008 |
| 7348281 | Method of filling structures for forming via-first dual damascene interconnects A method of forming via-first, dual damascene interconnect structures by using a gap-filling, bottom anti-reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating ... | 03/25/2008 |
| 7344972 | Photosensitive dielectric layer The invention provides a layer of photosensitive material that may be directly patterned. The photosensitive material may then be decomposed to leave voids or air gaps in the layer. This may provide a low dielectric constant layer with reduced resistance capacitance... | 03/18/2008 |
| 7338895 | Method for dual damascene integration of ultra low dielectric constant porous materials A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k ... | 03/04/2008 |
| 7335588 | Interconnect structure and method of fabrication of same A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask... | 02/26/2008 |
| 7335991 | Pattern forming structure, pattern forming method, device, electro-optical device, and electronic apparatus There is provided a barrier structure provided with a concave portion corresponding to a pattern formed out of a functional liquid, the barrier structure comprising: a first concave portion provided in the barrier to correspond to a first pattern; and a second conca... | 02/26/2008 |
| 7329602 | Wiring structure for integrated circuit with reduced intralevel capacitance A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated fr... | 02/12/2008 |
| 7329955 | Metal-insulator-metal (MIM) capacitor A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a substrate. A portion of the first metal layer is utilized as the lower plate of the MIM capacitor. An etch stop di... | 02/12/2008 |
| 7323407 | Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a ... | 01/29/2008 |
| 7319071 | Methods for forming a metallic damascene structure In damascene process integration, a reducing plasma is applied after the etch stop or barrier layer is opened over a copper layer. Currently known methods for opening barrier layers suffer from the disadvantage that they cause at least some of the underlying copper ... | 01/15/2008 |
