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| Number | Title | Issue Date |
| 7439177 | Method of manufacturing semiconductor device for improving contact hole filling characteristics while reducing parasitic capacitance of inter-metal dielectric In manufacturing a semiconductor device, a metal film is formed on a semiconductor substrate, and a high-temperature amorphous carbon film pattern for defining a wiring forming area is formed on the metal film. The metal film is etched by using the high-temperature ... | 10/21/2008 |
| 7411240 | Integrated circuits including spacers that extend beneath a conductive line Integrated circuit devices are fabricated by fabricating a conductive line on an insulating layer on an integrated circuit substrate. The conductive line includes a bottom adjacent the insulating layer, a top remote from the insulating layer and first and second sid... | 08/12/2008 |
| 7338897 | Method of fabricating a semiconductor device having metal wiring A method of fabricating a semiconductor device includes forming a metal wire on a substrate, forming an interlayer insulating film on the metal wire, forming a resist pattern on the interlayer insulating film, selectively etching the interlayer film to form a trench... | 03/04/2008 |
| 7271090 | Guard ring of a combination wafer or singulated die A combination wafer is manufactured by (i) forming a plurality of alternating dielectric and metal layers, (ii) forming a guard ring trench in the layers, (iii) forming a guard ring layer in the guard ring trench, and then repeating (i), (ii) with a slightly wider g... | 09/18/2007 |
| 7192862 | Semiconductor device and method of manufacturing the same A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) ... | 03/20/2007 |
| 7163890 | Methods of fabricating semiconductor device having slope at lower sides of interconnection hole with etch-stop layer Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the e... | 01/16/2007 |
| 7119442 | Semiconductor device A semiconductor device comprising a first insulating layer formed above a semiconductor substrate, and comprising a first insulating material, a second insulating material and a hole, a relative dielectric constant of the first insulating material being 3 or less, a... | 10/10/2006 |
| 7101786 | Method for forming a metal line in a semiconductor device Provided is a method for forming a metal line in a semiconductor device. The method forms round portions at top edges of an insulation film by means of a polymer and then etches the rest portion (i.e., sidewall parts) in an almost vertical direction, which makes it ... | 09/05/2006 |
| 6700211 | Method for forming conductors in semiconductor devices A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby ... | 03/02/2004 |
| 6693360 | Static type semiconductor memory device A memory cell of a static type semiconductor memory device includes a gate electrode of an MOS transistor formed on a main surface of semiconductor substrate via an insulator film, an interlayer insulator film covering the gate electrode, a set of contact... | 02/17/2004 |
| 6686228 | Semiconductor device and manufacturing method thereof It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (ino... | 02/03/2004 |
| 6670713 | Method for forming conductors in semiconductor devices A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby ... | 12/30/2003 |
| 6670267 | Formation of tungstein-based interconnect using thin physically vapor deposited titanium nitride layer A tungsten-based interconnect is created by first providing a structure with an opening (464/470) in a structure and then rounding the top edge of the opening. A titanium nitride layer (150) is physically vapor deposited to a thickness less than 30 nm, ty... | 12/30/2003 |
| 6664639 | Contact and via structure and method of fabrication The present invention is a contact/via comprising and its method of fabrication. The contact/via of the present invention includes a conductive film. An opening having a top and bottom is formed on the conductive film. The opening has a first sidewall and... | 12/16/2003 |
| 6663787 | Use of ta/tan for preventing copper contamination of low-k dielectric layers A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier lay... | 12/16/2003 |
| 6660630 | Method for forming a tapered dual damascene via portion with improved performance A method for selectively anisotropically a semiconductor feature to form a tapered sidewall profile including providing a semiconductor wafer including an anisotropically etched feature formed in at least one dielectric insulating layer including a relati... | 12/09/2003 |
| 6653733 | Conductors in semiconductor devices A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby ... | 11/25/2003 |
| 6653739 | Semiconductor device A contact plug 26 formed between adjacent two wirings 14 according to a self-aligning manner is provided. An interlayer oxide film 12 is provided on a substrate layer 10 conductive to the bottom face of the contact plug. A lower insulating film 32 formed ... | 11/25/2003 |
| 6649517 | Copper metal structure for the reduction of intra-metal capacitance A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as o... | 11/18/2003 |
| 6635585 | Method for forming patterned polyimide layer Within a method for forming a patterned polyimide layer, there is first provided a substrate. There is then formed over the substrate a blanket polyamic acid layer. There is then formed upon the blanket polyamic acid layer a patterned photoresist layer. T... | 10/21/2003 |
| 6632746 | Etching method, semiconductor and fabricating method for the same An organic/inorganic hybrid film represented by SiCx Hy Oz (x>0, yࣙ0, z>0) is plasma-etched with an etching gas containing fluorine, carbon and nitrogen. During the etching, a carbon component is eliminated from the surf... | 10/14/2003 |
| 6593235 | Semiconductor device with a tapered hole formed using multiple layers with different etching rates A semiconductor device having an improved contact hole through an interlayer insulator. A first insulating film comprising silicon nitride is deposited. A second insulating film comprising silicon oxide is deposited on the first insulating film. The depos... | 07/15/2003 |
| 6569785 | Semiconductor integrated circuit device having internal tensile and internal compression stress A semiconductor device has a structure that is capable of reducing warping of a semiconductor wafer when the semiconductor device is manufactured. The semiconductor device is manufactured by a method including the steps for forming an interlayer dielectri... | 05/27/2003 |
| 6563220 | Method for forming conductors in semiconductor devices A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby ... | 05/13/2003 |
| 6534403 | Method of making a contact and via structure The present invention is a contact/via comprising and its method of fabrication. The contact/via of the present invention includes a conductive film. An opening having a top and bottom is formed on the conductive film. The opening has a first sidewall and... | 03/18/2003 |
| 6524949 | Method of forming low-resistance contact electrodes in semiconductor devices There is formed on a semiconductor substrate a lamination of a first insulating film of nondoped silicon glass or the like and, on this first insulating film, a second insulating film of boron phosphor silicate glass or the like, with a conductor layer be... | 02/25/2003 |
| 6524875 | Method for manufacturing tapered opening using an anisotropic etch during the formation of a semiconductor device A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned secon... | 02/25/2003 |
| 6518191 | Method for etching organic film, method for fabricating semiconductor device and pattern formation method Etching is conducted on an organic film to be used as an interlayer insulating film by using plasma generated from an etching gas containing, as a principal constituent, a compound including carbon, hydrogen and nitrogen, such as methylamine.... | 02/11/2003 |
| 6503829 | Metal via contact of a semiconductor device and method for fabricating the same A metal via contact of a semiconductor device and a method for fabricating the same, wherein the method includes sequentially forming a first insulating layer, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride ... | 01/07/2003 |
| 6495470 | Contact and via fabrication technologies A method of forming a contact opening between two conductive features over a semiconductor substrate. Oxide spacers are formed adjacent to the conductive features. A doped oxide layer is then deposited over the semiconductor substrate. Finally, the contac... | 12/17/2002 |
| 6483142 | Dual damascene structure having capacitors This invention provides a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, a... | 11/19/2002 |
| 6483194 | Semiconductor device having capacitor and method thereof A semiconductor device includes a semiconductor substrate, a first interlayer dielectric film covering the semiconductor substrate, a second interlayer dielectric film covering the first interlayer dielectric, an opening having an upper-layer opening pene... | 11/19/2002 |
| 6475836 | Semiconductor device and manufacturing method thereof It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (ino... | 11/05/2002 |
| 6476496 | Semiconductor device and method of manufacturing the same An interconnection forming step provides an interconnection with an improved yield, a low cost and a high reliability. A semiconductor device includes an insulating layer formed on a silicon substrate and having a groove extending in a predetermined direc... | 11/05/2002 |
| 6458657 | Method of fabricating gate A method of fabricating a gate. A gate dielectric layer is formed, and a lower portion of a floating gate is formed encompassed by a first dielectric layer. Second dielectric layers with different etching rates are formed to cover the upper portion of the... | 10/01/2002 |
| 6458710 | Process for forming uniform multiple contact holes A process for defining uniform contact hole openings in an insulator layer, and in a top portion of a conductive layer, has been developed. The process features a series of isotropic and anisotropic, dry etch procedures, used to define an initial contact ... | 10/01/2002 |
| 6455427 | Method for forming void-free metallization in an integrated circuit A metallization structure and method for fabricating such a metallization structure are presented. The present method preferably includes forming a void within a metal layer. The void may have a void pressure level, which is preferably approximately equal... | 09/24/2002 |
| 6455403 | Shallow trench contact structure to solve the problem of schottky diode leakage A method for fabricating a Schottky diode using a shallow trench contact to reduce leakage current in the fabrication of an integrated circuit device is described. The method provides a simple and effective method for decreasing the possibility of forming... | 09/24/2002 |
| 6455410 | Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing thereof are provided wherein no hollow area is generated in a contact wiring plug which is formed in the interlayer insulation layer. According to the method of manufacturing of this semiconductor devic... | 09/24/2002 |
| 6452277 | Semiconductor device and manufacturing method thereof A silicon oxide film is formed to cover a polysilicon plug. A bowing shaped hole is formed. A barrier metal and a metal film are formed, which are successively subjected to prescribed anisotropic etching. Here, because of the RIE-lag effect, the etch rate... | 09/17/2002 |
