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| Number | Title | Issue Date |
| 7439173 | Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dum... | 10/21/2008 |
| 7427561 | Method for manufacturing semiconductor device A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; fo... | 09/23/2008 |
| 7422975 | Composite inter-level dielectric structure for an integrated circuit A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Nex... | 09/09/2008 |
| 7423283 | Strain-silicon CMOS using etch-stop layer and method of manufacture Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide ... | 09/09/2008 |
| 7419847 | Method for forming metal interconnection of semiconductor device A method for forming a metal interconnection of a semiconductor device avoids over-etching and under-etching through the use of the “self-stop” function of a nitridation layer, to prevent the occurrence of openings and voids in a copper interconnection and to ob... | 09/02/2008 |
| 7420275 | Boron-doped SIC copper diffusion barrier films Copper diffusion barrier films having a boron-doped silicon carbide layer with at least 25% boron by atomic weight of the layer composition have advantages for semiconductor device integration schemes. The films have an integration worthy etch selectivity to carbon ... | 09/02/2008 |
| 7411301 | Semiconductor integrated circuit device In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried... | 08/12/2008 |
| 7410895 | Methods for forming interconnect structures A method for forming an interconnect structure. A substrate is provided with a low-k dielectric layer thereon. At least one conductive feature is then formed in the low-k dielectric layer. A cap layer is formed overlying the low-k dielectric layer, and the conductiv... | 08/12/2008 |
| 7405150 | Post passivation interconnection schemes on top of the IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 07/29/2008 |
| 7402532 | Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is ... | 07/22/2008 |
| 7394157 | Integrated circuit and seed layers Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the i... | 07/01/2008 |
| 7361613 | Semiconductor device, manufacture and evaluation methods for semiconductor device, and process condition evaluation method A gate insulating film made of silicon oxynitride is disposed on the partial surface area of a semiconductor substrate. A gate electrode is disposed on the gate insulating film. Source and drain regions are disposed on both sides of the gate electrode. An existence ... | 04/22/2008 |
| 7358188 | Method of forming conductive metal silicides by reaction of metal with silicon The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a ni... | 04/15/2008 |
| 7352065 | Semiconductor devices having amorphous silicon-carbon dielectric and conducting layers A method for fabricating a semiconductor device having a plurality of layers, depositing a first layer comprising a medium-k dielectric barrier layer on one of the plurality of layers, depositing a second layer comprising a low-k dielectric layer on the first layer,... | 04/01/2008 |
| 7351648 | Methods for forming uniform lithographic features Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conforma... | 04/01/2008 |
| 7348281 | Method of filling structures for forming via-first dual damascene interconnects A method of forming via-first, dual damascene interconnect structures by using a gap-filling, bottom anti-reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating ... | 03/25/2008 |
| 7342315 | Method to increase mechanical fracture robustness of porous low k dielectric materials The present invention provides an insulating layer 100 for an integrated circuit 110 comprising a porous silicon-based dielectric layer 120 located over a substrate 130. The insulating layer comprises a densified layer 140 comprisi... | 03/11/2008 |
| 7341943 | Post etch copper cleaning using dry plasma A method for post-etch copper cleaning uses a hydrogen plasma with a trace gas additive constituting about 3-10 percent of the plasma by volume to clean a copper surface exposed by etching. The trace gas may be atomic nitrogen or other species having an atomic mass ... | 03/11/2008 |
| 7319068 | Method of depositing low k barrier layers A method is provided for processing a substrate including providing a processing gas comprising an organosilicon compound comprising a phenyl group to the processing chamber, and reacting the processing gas to deposit a low k silicon carbide barrier layer useful as ... | 01/15/2008 |
| 7314831 | Copper line of semiconductor device and method for forming the same A copper line on a semiconductor device and a method for forming the same is disclosed, wherein an insulating layer is deposited so as to minimize the dishing of IMD without using a dummy area when performing the planarization process. The method of forming the copp... | 01/01/2008 |
| 7301236 | Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dum... | 11/27/2007 |
| 7282437 | Insulating tube, semiconductor device employing the tube, and method of manufacturing the same An insulating tube includes a underlying insulating film, a first sidewall insulating film disposed on the underlying insulating film, a second sidewall insulating film disposed on the underlying insulating film, opposite to the first sidewall insulating film so as ... | 10/16/2007 |
| 7273823 | Situ oxide cap layer development A method of processing a substrate including depositing a low dielectric constant film comprising silicon, carbon, and oxygen on the substrate and depositing an oxide rich cap on the low dielectric constant film is provided. The low dielectric constant film is depos... | 09/25/2007 |
| 7271487 | Semiconductor device and method of manufacturing the same The present invention is to improve yield and reliability in a wiring step of a semiconductor device. When an Al wiring on an upper layer is connected through an connection pillar onto an Al wiring on a lower layer embedded in a groove formed on an interlayer insula... | 09/18/2007 |
| 7253110 | Method and apparatus for forming a barrier metal layer in semiconductor devices A method and apparatus for forming a barrier metal layer in semiconductor devices are disclosed. A disclosed method for forming a barrier metal layer in a semiconductor device forms an interlayer insulating layer on a front face of a semiconductor substrate having a... | 08/07/2007 |
| 7220665 | H plasma treatment Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive l... | 05/22/2007 |
| 7220685 | Method for depositing porous films A processing method for depositing porous silica and doped silica films is provided. The method uses a cyclic scheme wherein each cycle comprises first codepositing silica with silicon, then selectively removing the silicon from the codeposit to form a porous struct... | 05/22/2007 |
| 7211519 | Method for manufacturing semiconductor device After an SiC film (4), an SiO2 film (5) and a silicon nitride film (6) are formed sequentially on an organic low dielectric constant film (3), by performing O2 plasma processing to a surface of the silicon nitride fi... | 05/01/2007 |
| 7205249 | CVD plasma assisted low dielectric constant films A method and apparatus for depositing a low dielectric constant film by reaction of an organosilane or organosiloxane compound and an oxidizing gas at a low RF power level from 10–250 W. The oxidized organosilane or organosiloxane film has good barrier properties ... | 04/17/2007 |
| 7202185 | Silica thin films produced by rapid surface catalyzed vapor deposition (RVD) using a nucleation layer An method employing atomic layer deposition (ALD) and rapid vapor deposition (RVD) techniques conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film has a low dielectric constant and a high degree of surfac... | 04/10/2007 |
| 7179758 | Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in t... | 02/20/2007 |
| 7166531 | VLSI fabrication processes for introducing pores into dielectric materials Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conduct... | 01/23/2007 |
| 7153735 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film 9, 10 above a semiconductor substrate 1; forming a capacitor Q having a lower electrode 11a, a dielectric film 13a, and ... | 12/26/2006 |
| 7154183 | Semiconductor device having multilevel interconnection A semiconductor device having a multilevel interconnection encompasses (a) a subject level interconnect, (b) a subject interlevel insulator disposed on the subject level interconnect, (c) a connecting via-plug buried in the subject interlevel insulator, the bottom s... | 12/26/2006 |
| 7148157 | Use of phoslon (PNO) for borderless contact fabrication, etch stop/barrier layer for dual damascene fabrication and method of forming phoslon A method of forming phoslon (PNO) comprising the following steps. A CVD reaction chamber having a reaction temperature of from about 300 to 600° C. is provided. From about 10 to 200 sccm PH3 gas, from about 50 to 4000 sccm N2 gas and from abou... | 12/12/2006 |
| 7148155 | Sequential deposition/anneal film densification method A silicon dioxide-based dielectric layer is formed on a substrate surface by a sequential deposition/anneal technique. The deposited layer thickness is insufficient to prevent substantially complete penetration of annealing process agents into the layer and migratio... | 12/12/2006 |
| 7141502 | Slurry-less polishing for removal of excess interconnect material during fabrication of a silicon integrated circuit A method for Chemical-Mechanical Polishing utilizes a two step process. The first step utilizes a slurry with abrasive particles which become embedded into a conditioned polishing pad having small cavities in the surface. During the second step the slurry flow is di... | 11/28/2006 |
| 7135402 | Sealing pores of low-k dielectrics using CH A semiconductor method of manufacturing involving porous and/or carbon containing, low-k dielectrics is provided. The method includes forming a hydrocarbon of the general composition CxHy on the surface of the low-k dielectric. The hydrocarbon ... | 11/14/2006 |
| 7129189 | Aluminum phosphate incorporation in silica thin films produced by rapid surface catalyzed vapor deposition (RVD) An method employing atomic layer deposition (ALD) and rapid vapor deposition (RVD) techniques conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film applies a phosphate-doped silicate film using atomic laye... | 10/31/2006 |
| 7119009 | Semiconductor device with dual damascene wiring A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trenc... | 10/10/2006 |
