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| Number | Title | Issue Date |
| 7439116 | Apparatus and method for forming polycrystalline silicon thin film Apparatus and method for forming a polycrystalline silicon thin film by converting an amorphous silicon thin film into the polycrystalline silicon thin film using a metal are provided. The method includes: a metal nucleus adsorbing step of introducing a vapor phase ... | 10/21/2008 |
| 7436075 | Ion beam irradiation apparatus and ion beam irradiation method The ion beam irradiation apparatus has a vacuum chamber 10, an ion source 2, a substrate driving mechanism 30, rotation shafts 14, arms 12, and a motor. The ion source 2 is disposed inside the vacuum chamber 10, and e... | 10/14/2008 |
| 7435667 | Method of controlling polysilicon crystallization A heat sink layer is formed on portions of a substrate, and then an amorphous silicon layer is formed thereon. The heat coefficient of the sink layer is greater than that of the substrate. When an excimer laser heats the amorphous silicon layer to crystallize the am... | 10/14/2008 |
| 7413939 | Method of growing a germanium epitaxial film on insulator for use in fabrication of CMOS integrated circuit A method of fabricating a silicon-germanium CMOS includes preparing a silicon substrate wafer; depositing an insulating layer on the silicon substrate wafer; patterning and etching the insulating layer; depositing a layer of polycrystalline germanium on the insulati... | 08/19/2008 |
| 7410891 | Method of manufacturing a superjunction device A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etche... | 08/12/2008 |
| 7384810 | Image display device and method for manufacturing the same Only a region where TFTs constituting a high-performance circuit will be disposed in a precursor semiconductor film PCS on an insulating substrate GLS with an insulating layer UCL serving as an undercoat is irradiated with a first energy beam LSR so as to be poly-cr... | 06/10/2008 |
| 7371655 | Method of fabricating low-power CMOS device A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The ... | 05/13/2008 |
| 7309637 | Method to enhance device performance with selective stress relief A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over ... | 12/18/2007 |
| 7238568 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 07/03/2007 |
| 7154159 | Trench isolation structure and method of forming the same A trench isolation structure and a method of forming a trench isolation structure are provided. The method includes providing a substrate having a trench. A polysilicon liner is formed in the trench. A dielectric layer, such as spin-on glass, is formed in the trench... | 12/26/2006 |
| 7135391 | Polycrystalline SiGe junctions for advanced devices A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers a... | 11/14/2006 |
| 7109110 | Method of manufacturing a superjunction device A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etche... | 09/19/2006 |
| 6696349 | STI leakage reduction A semiconductor device is provided having at least two neighboring transistors and an STI region therebetween. The STI region is provided with a voltage bias to minimize subthreshold leakage current between the neighboring transistors. A method of fabrica... | 02/24/2004 |
| 6693018 | Method for fabricating DRAM cell transistor having trench isolation structure The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion o... | 02/17/2004 |
| 6683363 | Trench structure for semiconductor devices A MOS trench structure integrated with a semiconductor device for enhancing the breakdown characteristics of the semiconductor device, comprises a semiconductor substrate, a plurality of parallel trenches formed in the semiconductor substrate, a periphera... | 01/27/2004 |
| 6656817 | Method of filling isolation trenches in a substrate Disclosed herein is a method of filling isolation trenches in a substrate. The method includes anisotropically etching trenches in a surface of a substrate and partially filling the trenches with a deposited oxide. As a consequence of the deposition, the ... | 12/02/2003 |
| 6653182 | Process for forming deep and shallow insulative regions of an integrated circuit Prior fabricating the transistors, a phase of forming a deep insulative trench in the substrate is followed by a phase of forming a shallow insulative trench in the substrate and extending the deep trench. The phase of forming the deep trench includes coa... | 11/25/2003 |
| 6649487 | Method of manufacturing semiconductor integrated circuit device A method of manufacturing a semiconductor integrated circuit device according to this invention, comprises a step of forming in a semiconductor substrate a deep groove for trench isolation with an aspect ratio of greater than 1, a step of burying a first ... | 11/18/2003 |
| 6646320 | Method of forming contact to poly-filled trench isolation region Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An "emitter window" is masked directly over the polysilicon trench fill. Heavily doped single ... | 11/11/2003 |
| 6638814 | Method for producing an insulation A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an insulation. The method creates both the storage capacitors and the insulation by forming trenches in th... | 10/28/2003 |
| 6632723 | Semiconductor device A semiconductor device is disclosed, which includes a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of wh... | 10/14/2003 |
| 6624045 | Thermal conducting trench in a seminconductor structure and method for forming the same The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a co... | 09/23/2003 |
| 6624044 | Method for manufacturing semiconductor device having trench filled with polysilicon First, a trench of a semiconductor substrate is filled with a polysilicon film deposited on the surface of the semiconductor substrate. A selective thin film having etching selectivity with respect to the polysilicon film is formed on the polysilicon film... | 09/23/2003 |
| 6610143 | Method of manufacturing a semiconductor component A method of manufacturing a semiconductor component includes forming an electrically insulative layer (220) over a semiconductor substrate where a first portion of the electrically insulative layer is located over a first region (560) of the semiconductor... | 08/26/2003 |
| 6610578 | Methods of manufacturing bipolar transistors for use at radio frequencies A bipolar transistor of type NPN has an active region at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas. The active region is partly covered by an electrica... | 08/26/2003 |
| 6607959 | Integrated circuit devices having trench isolation structures and methods of fabricating the same Integrated circuit devices include an integrated circuit substrate having a face and a trench in the face. The trench has a trench sidewall and a trench floor. A first insulating layer is provided on the trench sidewall that exposes at least part of the t... | 08/19/2003 |
| 6599812 | Manufacturing method for a thick oxide layer A method for manufacturing a thick oxide layer on a semiconductive substrate is presented. The method comprises the formation of at least one layer of dielectric material on said substrate, followed by formation of a plurality of trench regions of a prede... | 07/29/2003 |
| 6593242 | Process for planarization and recess etching of integrated circuits The invention is directed to a process for forming a recess in at least one polysilicon overfilled trench in an integrated circuit. The process includes the following steps: uniformly etching the polysilicon overfill layer; stopping the etching before the... | 07/15/2003 |
| 6566227 | Strap resistance using selective oxidation to cap DT poly before STI etch A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (1... | 05/20/2003 |
| 6566228 | Trench isolation processes using polysilicon-assisted fill Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first ... | 05/20/2003 |
| 6563193 | Semiconductor device A semiconductor device comprises a substrate the surface of which is formed of an insulation region, a high resistance active layer of a first conductivity type formed on the substrate, a first semiconductor region of the first conductivity type having an... | 05/13/2003 |
| 6559030 | Method of forming a recessed polysilicon filled trench A method of forming a recessed polysilicon contact is provided. The method includes: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidiz... | 05/06/2003 |
| 6551944 | Process for manufacturing a semiconductor material wafer comprising single-Crystal regions separated by insulating material regions A process including the steps of: carrying out a directional etching in a semiconductor material body to form trenches having a first width; carrying out an isotropic etching of the semiconductor material body under the trenches to form cavities having a ... | 04/22/2003 |
| 6551868 | Vertical power component manufacturing method A method for manufacturing a vertical power component on a silicon wafer, including the steps of growing a lightly-doped epitaxial layer of a second conductivity type on the upper surface of a heavily-doped substrate of a first conductivity type, the epit... | 04/22/2003 |
| 6541839 | Microelectronics structure comprising a low voltage part provided with protection against a high voltage part and method for obtaining said protection A microelectronic structure with a low voltage part and high voltage part, such that the low voltage part is protected against the high voltage part and process of obtaining this protection. The structure includes at least one low-voltage element (2) and at le... | 04/01/2003 |
| 6538294 | Trenched semiconductor device with high breakdown voltage An arrangement in a semiconductor component includes a highly doped layer on a substrate layer and is delimited by at least one trench extending from the surface of the component through the highly doped layer. A sub-layer between the substrate layer and ... | 03/25/2003 |
| 6521538 | Method of forming a trench with a rounded bottom in a semiconductor device In a method for manufacturing a semiconductor device, first, a trench is formed on a semiconductor substrate by anisotropic etching, and a reaction product is produced and deposited on the inner wall of the trench during the anisotropic etching. Then, iso... | 02/18/2003 |
| 6518145 | Methods to control the threshold voltage of a deep trench corner device A method of manufacturing a semiconductor trench device comprises forming a dielectric on a substrate, the dielectric having an underlying oxide layer adjacent the substrate, etching a trench in the dielectric and the substrate, forming a recess in the un... | 02/11/2003 |
| 6503793 | Method for concurrently forming an ESD protection device and a shallow trench isolation region The present invention provides a method of forming a trench capacitor in an input/output region and a trench isolation structure in an active device region and a method of manufacturing an integrated circuit using the aforementioned method of forming. The... | 01/07/2003 |
| 6504232 | Integrated circuit components thereof and manufacturing method The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or... | 01/07/2003 |
