Class 257/E21.558 - Introducing both types of electrical active impurities in local oxidation region solely for forming channel stoppers, e.g., for isolation of complementary doped regions (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.557. This subclass
No. of patents: 94
Last issue date: 06/26/2007

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Number	Title	Issue Date
7235460	Method of forming active and isolation areas with split active patterning A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on t...	06/26/2007
6815762	Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conduc...	11/09/2004
6489657	Semiconductor device with improved channel stopper A semiconductor device comprising a high withstand voltage MOS transistor of an offset drain/offset source structure easing a high electric field generated between a channel and a parasitic channel stopper in an operating state and preventing changes of a...	12/03/2002
6472279	Method of manufacturing a channel stop implant in a semiconductor device The present invention provides a method of manufacturing a semiconductor device, and a related method manufacturing an integrated circuit. In one embodiment, the method of manufacturing a semiconductor device includes creating a source/drain region betwee...	10/29/2002
6465295	Method of fabricating a semiconductor device A semiconductor device fabrication method comprises the steps of forming a gate insulating film on a surface of a semiconductor substrate, forming a polysilicon film on the gate insulating film, and implanting B or BF2 impurity ions into the po...	10/15/2002
6326252	Method for fabricating MOS transistor having dual gate Methods of forming a MOS transistor having dual gates minimizes impurity channeling and diffusion that can occur during impurity injection and activating processes. A method of fabricating the transistor includes the steps of forming a first conduction ty...	12/04/2001
6268298	Method of manufacturing semiconductor device In a method of manufacturing a semiconductor device, after performing ion-implantation and before forming an oxide film, a silicon substrate is disposed within a furnace to undergo a heat treatment at a temperature equal to or higher than 950° C. for a s...	07/31/2001
6198139	Complementary MOS device A p- epitaxial layer is formed on the main surface of a p+ silicon substrate. A p-type impurity region is formed extending from the main surface into epitaxial layer. P-type impurity region has a first region having a relatively larg...	03/06/2001
6187643	Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI) Methods are provided for fabrication of a circuit on a substrate. After formation of gate electrodes, sidewall spacers are formed on the sides of the gate electrodes. Source/drain extensions and source/drain regions of p-type devices are implanted through...	02/13/2001
6133081	Method of forming twin well A method of forming a twin well includes the steps of: forming a field oxide layer on a semiconductor substrate to define active regions of a device, and forming a first mask which exposes a predetermined active region of the semiconductor substrate; ion-...	10/17/2000
6077735	Method of manufacturing semiconductor device A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for se...	06/20/2000
6069059	Well-drive anneal technique using preplacement of nitride films for enhanced field isolation A method of forming an isolation structure comprising forming n-type areas and/or p-type areas implanted respectively therein on a first surface of the substrate. A pad oxide film is grown on the substrate first surface covering the p-wells and/or n-wells...	05/30/2000
6069048	Reduction of silicon defect induced failures as a result of implants in CMOS and other integrated circuits A technique for reducing silicon defect induced transistor failures, such as latch-up, in a CMOS or other integrated circuit structure includes fabricating the integrated circuit structure on a substrate and implanting a buried layer beneath a surface of ...	05/30/2000
6054342	Method of making integrated circuits with tub-ties An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first condu...	04/25/2000
6001701	Process for making bipolar having graded or modulated collector A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to there...	12/14/1999
5998828	Semiconductor device having nitrogen introduced in its polysilicon gate In a semiconductor device and a method of manufacturing the same according to the present invention, a trade-off relationship between threshold values and a diffusion layer leakage is eliminated and it is not necessary to form gate oxide films at more tha...	12/07/1999
5972746	Method for manufacturing semiconductor devices using double-charged implantation The invention provides an isolation technique using fewer process steps and a double charged implantation step (141) for defining a well region (139) of a CMOS integrated circuit device. The invention provides steps of providing a semiconductor substrate ...	10/26/1999
5945715	Semiconductor memory device having a memory cell region and a peripheral circuit region and method of manufacturing the same LOCOS isolation is used for isolation between wells in a memory cell part, and an isolation width is reduced, so that a degree of integration of memory cells is improved in a semiconductor memory device. At the memory cell part in the semiconductor memory...	08/31/1999
5927991	Method for forming triple well in semiconductor device An improved method for forming a triple well of a semiconductor device which is capable of more simply and easily forming a triple well without removing an anti-oxidation film. In addition, it is possible to reduce the amount of the removal of the field o...	07/27/1999
5926704	Efficient method for fabricating P-wells and N-wells A method forms, in a CMOS semiconductor substrate, P- and N-wells having independently optimized field regions and active regions. In one embodiment, P- and N-wells are formed by (i) creating in successive steps the field regions of the P- and N-wells; (i...	07/20/1999
5895258	Semiconductor device fabrication method A semiconductor fabrication method for forming an insulation film and a first anti-oxidation film sequentially on a substrate which is sectioned into each of a peri region and a cell region. An active pattern is formed in the cell region and a first field...	04/20/1999
5831313	Structure for improving latch-up immunity and interwell isolation in a semiconductor device A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located b...	11/03/1998
5789287	Method of forming field isolation in manufacturing a semiconductor device This invention discloses a method of manufacturing a semiconductor device, especially a method of forming field isolation, in which a portion of an active region around a field oxide film is highly-doped with the same type impurities as channel-stop impur...	08/04/1998
5773336	Methods of forming semiconductor active regions having channel-stop isolation regions therein Methods of forming semiconductor active regions having channel-stop regions therein include the steps of forming an oxide layer and first nitride layer on a face of a semiconductor substrate and then patterning the first nitride layer to expose first port...	06/30/1998
5696399	Process for manufacturing MOS-type integrated circuits A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on ...	12/09/1997
5691564	Semiconductor device with high speed operation and high integration A semiconductor device manufactured by isolating an element by forming an insulating film on the surface of a semiconductor substrate at an element isolation region, selectively forming a resist film at a second region on the surface of the semiconductor ...	11/25/1997
5686348	Process for forming field isolation structure with minimized encroachment effect A method for minimizing the impurity encroachment effect of the field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a first layer and a second layer are deposited on a laminate comprising a substrate having...	11/11/1997
5675171	Integrated insulated gate field effect transistors with thin insulation region between field insulation regions Disclosed is a semiconductor device, which has: a first device-separating insulating film which is formed on a semiconductor substrate and extends in a first(Y) direction; a second device-separating insulting film which is formed on said semiconductor sub...	10/07/1997
5663080	Process for manufacturing MOS-type integrated circuits A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on ...	09/02/1997
5637524	Method for forming wells of semiconductor device A method for forming wells of a semiconductor device, being capable of removing the topology between n- and p-well regions. The method of the present invention provides a twin well structure wherein the n-well region has a higher level than the p-well reg...	06/10/1997
5614434	Method for minimizing the encroachment effect of field isolation structure A method for minimizing the impurity encroachment effect of field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a sacrificial layer is deposited on a laminate comprising a substrate having thereon stacked l...	03/25/1997
5504364	CMOS locos isolation for self-aligned NPN BJT in a BiCMOS process A method of fabricating BiCMOS devices, and the resultant BiCMOS device, are disclosed. According to the present invention, over-etching to the substrate on the deposited polysilicon emitter is prevented by providing additional oxide beneath a polysilicon...	04/02/1996
5501993	Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation CMOS vertically modulated wells are constructed by using clustered MeV ion implantation to form a structure having a buried implanted layer for laterial isolation....	03/26/1996
5489795	Semiconductor integrated circuit device having double well structure A semiconductor device has a first P type well region (11) formed on an N type semiconductor substrate (10) and a second N type well region (12) formed so as to enclose the first well region. A third N type well region (13) formed on the semiconductor sub...	02/06/1996
5484742	Process for preparing a semiconductor device with a narrow-channel MOS transistor A second photo-resist film 6a is formed on first photo-resist film 5a which functions as a mask for etching an oxidation resistant silicon nitride film 3 in a region in which a narrow-channel MOS transistor is to be formed. Ions having p-type are implante...	01/16/1996
5478759	Method of manufacturing semiconductor device with retrograde wells A thick isolation oxide film is selectively formed on a surface of a silicon substrate so as to isolate an element formation region. Ions are implanted into a region in silicon substrate through the thick isolation oxide film. Thus, retrograde wells, havi...	12/26/1995
5434099	Method of manufacturing field isolation for complimentary type devices The method requires fewer process steps. A nitride layer and a first overlying photoresist are deposited on a semiconductor substrate having wells of different impurity types. The resist layer is developed and to cover first type well and the device area ...	07/18/1995
5422301	Method of manufacturing semiconductor device with MOSFET A method of manufacturing a semiconductor device with MOSFETs including the steps of forming an anti-oxidation film pattern over an element forming region of a semiconductor substrate, selectively oxidizing a region not covered with the anti-oxidation fil...	06/06/1995
5399895	Semiconductor device and method of manufacturing thereof A LOCOS oxide film is provided in a main surface of a semiconductor substrate for isolating an element region from another element region. A channel cut layer formed of a P-type impurity is provided under the element region. A P+ impurity regio...	03/21/1995
5396096	Semiconductor device and manufacturing method thereof In a semiconductor device, a FET and an isolation are provided on a semiconductor substrate and a channel stop region is provided under the isolation. At least a region to which a high voltage is applied of a source region and a drain region of the FET is...	03/07/1995

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Class 257/E21.558 - Introducing both types of electrical active impurities in local oxidation region solely for forming channel stoppers, e.g., for isolation of complementary doped regions (EPO)