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| Number | Title | Issue Date |
| 7436030 | Strained MOSFETs on separated silicon layers A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench in... | 10/14/2008 |
| 7405461 | Semiconductor device and method for manufacturing semiconductor device A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silico... | 07/29/2008 |
| 7396729 | Methods of forming semiconductor devices having a trench with beveled corners A semiconductor device is formed by providing a substrate. A trench is formed in the substrate. Beveled surfaces are formed at upper portions of sidewalls of the trench opposite a bottom surface of the trench, respectively. An oxide layer is formed in the trench suc... | 07/08/2008 |
| 7390717 | Trench power MOSFET fabrication using inside/outside spacers A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are for... | 06/24/2008 |
| 7391096 | STI structure An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching the first nitride layer, the pad oxide layer and the substrate. An o... | 06/24/2008 |
| 7358587 | Semiconductor structures In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and compr... | 04/15/2008 |
| 7339252 | Semiconductor having thick dielectric regions A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second... | 03/04/2008 |
| 7279396 | Methods of forming trench isolation regions with nitride liner The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is form... | 10/09/2007 |
| 7273792 | Semiconductor device and fabricating method thereof A semiconductor device including a semiconductor substrate, a device isolation region formed by filling a trench in the semiconductor substrate with dielectric material and defining device regions in the semiconductor substrate. The trench has a rounded upper edge, ... | 09/25/2007 |
| 7223698 | Method of forming a semiconductor arrangement with reduced field-to active step height A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. T... | 05/29/2007 |
| 7172910 | Web fabrication of devices Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to forming an assembly using different sized blocks in either a flexible or rigid substrate. ... | 02/06/2007 |
| 7154159 | Trench isolation structure and method of forming the same A trench isolation structure and a method of forming a trench isolation structure are provided. The method includes providing a substrate having a trench. A polysilicon liner is formed in the trench. A dielectric layer, such as spin-on glass, is formed in the trench... | 12/26/2006 |
| 6887767 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device including forming a buffer film on a semiconductor substrate, forming a element partitioning trench, forming a oxidized film on the surface of the element partitioning trench, and washing the semiconductor substrate ... | 05/03/2005 |
| 6713780 | Process using poly-buffered STI A method of providing a substantially planar trench isolation region having substantially rounded corners, said method comprising the steps of: (a) forming a film stack on a surface of a substrate, said film stack comprising an oxide layer, a polysilicon layer and a... | 03/30/2004 |
| 6699773 | Shallow trench isolation type semiconductor device and method of forming the same A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the et... | 03/02/2004 |
| 6699772 | Hybrid trench isolation technology for high voltage isolation using thin field oxide in a semiconductor process A method for creating a trench for high voltage isolation begins by forming a trench in the substrate having sidewalls and a bottom surface. Spacers are formed along the sidewalls of a trench with the spacers partially covering the bottom surface. A barri... | 03/02/2004 |
| 6682985 | Semiconductor device and manufacturing method thereof A semiconductor device as well as a method of manufacturing a semiconductor device wherein a wide trench separation band is formed without causing the scooping out of the silicon substrate can be gained. The process is provided with the step of forming a multi... | 01/27/2004 |
| 6683364 | Integrated circuit devices including an isolation region defining an active region area and methods for manufacturing the same Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is ... | 01/27/2004 |
| 6682967 | Semiconductor device and method of making the same A semiconductor device comprises a semiconductor substrate, a p-type well formed in the semiconductor substrate, an n-type well formed in the semiconductor substrate and positioned contiguous to the p-type well, an n-type diffused region formed in the p-t... | 01/27/2004 |
| 6682987 | METHODS OF FORMING A TRENCH ISOLATION REGION IN A SUBSTRATE BY REMOVING A PORTION OF A LINER LAYER AT A BOUNDARY BETWEEN A TRENCH ETCHING MASK AND AN OXIDE LAYER IN A TRENCH AND INTEGRATED CIRCUIT DEVICES FORMED THEREBY A trench isolation region is formed in a substrate by forming a trench-etching mask on the substrate. A trench is formed by etching the substrate through the trench-etching mask. An oxide layer is formed on sidewall and bottom surfaces of the trench. A li... | 01/27/2004 |
| 6682986 | Method of forming shallow trench isolation and method of manufacturing a semiconductor device using the same A method of forming a shallow trench isolation of a semiconductor device, includes providing a semiconductor substrate including field and active regions; forming a first insulating layer and a mask layer on the active region that expose the field region;... | 01/27/2004 |
| 6670279 | Method of forming shallow trench isolation with rounded corners and divot-free by using in-situ formed spacers A method of fabricating an STI structure comprising the following steps. A silicon structure having a pad oxide layer formed thereover is provided. A hard mask layer is formed over the pad oxide layer. The hard mask layer and the pad oxide layer are patte... | 12/30/2003 |
| 6667224 | Method to eliminate inverse narrow width effect in small geometry MOS transistors A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow wid... | 12/23/2003 |
| 6656845 | Method for forming semiconductor substrate with convex shaped active region Within a method for fabricating a semiconductor substrate while employing formed thereover a mask layer there is first employed the mask layer as an etch mask layer for forming a pair of isolation trenches within the semiconductor substrate and then later... | 12/02/2003 |
| 6649487 | Method of manufacturing semiconductor integrated circuit device A method of manufacturing a semiconductor integrated circuit device according to this invention, comprises a step of forming in a semiconductor substrate a deep groove for trench isolation with an aspect ratio of greater than 1, a step of burying a first ... | 11/18/2003 |
| 6642124 | Semiconductor device and manufacturing method thereof The present invention provides a semiconductor device that reduces the junction leak current and achieves an improvement in the reliability of the gate oxide film by minimizing divot formation and the occurrence of a kink and a method of manufacturing suc... | 11/04/2003 |
| 6620703 | Method of forming an integrated circuit using an isolation trench having a cavity formed by reflowing a doped glass mask layer Isolation characteristics of an isolation trench can be enhanced. Elements to be isolated by an isolation trench (STI 2) are formed in active semiconductor regions shown by arrows 30 and 31 on a semiconductor substrate 1. The STI 2 is filled with SiOF.... | 09/16/2003 |
| 6602745 | Field effect transistor and method of fabrication An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge ... | 08/05/2003 |
| 6599810 | Shallow trench isolation formation with ion implantation An insulated trench isolation structure is formed by ion implanting impurities proximate to the trench edges for enhancing the oxidation rate and, hence, increasing the thickness of the oxide at the trench edges. Embodiments include ion implanting impurit... | 07/29/2003 |
| 6593206 | Isolation region forming methods In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending ther... | 07/15/2003 |
| 6589854 | Method of forming shallow trench isolation A method of forming a shallow trench isolation structure. A pad oxide layer and a mask layer are sequentially formed over a substrate. A portion of the pad oxide layer, mask layer and substrate are removed to form a trench in the substrate. A first stage ... | 07/08/2003 |
| 6589853 | Method of forming a trench isolation structure having a second nitride film A semiconductor device including an insulating film (6) embedded in a concave portion, such as a trench (T) formed on a semiconductor substrate (1) is disclosed. A method of forming a trench isolation structure may include forming a mask layer having a pr... | 07/08/2003 |
| 6586314 | Method of forming shallow trench isolation regions with improved corner rounding A method of forming a shallow trench isolation (STI), region in a semiconductor substrate featuring a process sequence that results in desired rounded corners for the sides of active device regions located butting the STI region, has been developed. The p... | 07/01/2003 |
| 6579768 | Field effect transistor and method of fabrication An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge ... | 06/17/2003 |
| 6580117 | Non-volatile semiconductor memory device and method of manufacturing the same A non-volatile semiconductor memory device includes a plurality of trenches for element-isolation formed on the main surface of a semiconductor substrate, a nitrided silicon layer formed along the wall surface of the trench, a silicon oxide film for eleme... | 06/17/2003 |
| 6576558 | High aspect ratio shallow trench using silicon implanted oxide A trench is etched through the layers of pad oxide and silicon nitride that have been deposited on a substrate, the patterned layer of photoresist is left in place. A tilt angle nitrogen implant is performed into the surface of the substrate, a deep shall... | 06/10/2003 |
| 6566224 | Process for device fabrication The invention is a process for device fabrication that utilizes shallow trench isolation. The process involves the steps of forming an oxidation barrier region, e.g., silicon nitride, above a silicon substrate, providing an opening in the oxidation barrie... | 05/20/2003 |
| 6566207 | Semiconductor device fabricating method A method of fabricating a semiconductor device in which a LOCOS profile characteristic is applied to a normal shallow trench isolation (STI) structure thereby lowering compressive stress that is concentrated on the side of the STI and preventing a thinnin... | 05/20/2003 |
| 6566727 | N2O nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench. The first oxide layer is subjected to a nitrogen-oxide gas a... | 05/20/2003 |
| 6566226 | Semiconductor device and fabrication process thereof, method of forming a device isolation structure In a semiconductor device having an STI structure, a space is formed by causing a recession in an oxide film on a surface of a substrate with regard to a sidewall surface of a device isolation trench at an edge of the device isolation trench, and a Si fil... | 05/20/2003 |
