Class 257/E21.548 - Concurrent filling of plurality of trenches having different trench shape or dimension, e.g., rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.546. This subclass
No. of patents: 451
Last issue date: 10/21/2008

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Number	Title	Issue Date
7439604	Method of forming dual gate dielectric layer A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer ...	10/21/2008
7420259	Semiconductor device having two-layered charge storage electrode A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in...	09/02/2008
7416942	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device is provided. The method includes successively forming a first silicon film and a mask film above a semiconductor substrate through a gate insulating film, forming a plurality of trenches in the first silicon film and...	08/26/2008
7407897	Capacitor of analog semiconductor device having multi-layer dielectric film and method of manufacturing the same In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage ...	08/05/2008
7407875	Low resistance contact structure and fabrication thereof Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of ...	08/05/2008
7405461	Semiconductor device and method for manufacturing semiconductor device A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silico...	07/29/2008
7402499	Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widt...	07/22/2008
7393789	Protective coating for planarization Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolida...	07/01/2008
7393737	Semiconductor device and a method of manufacturing the same A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high...	07/01/2008
7393750	Method for manufacturing a semiconductor device Embodiments relate to a method of manufacturing a semiconductor device. According to embodiments, the method may include forming a first and a second insulating layer on a semiconductor substrate of which an active area and an isolation region are defined, forming a...	07/01/2008
7390717	Trench power MOSFET fabrication using inside/outside spacers A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are for...	06/24/2008
7387940	Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ...	06/17/2008
7384825	Methods of fabricating phase change memory elements having a confined portion of phase change material on a recessed contact Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall compri...	06/10/2008
7381612	Method for manufacturing semiconductor device with recess channels and asymmetrical junctions Disclosed is a method for manufacturing a semiconductor device having recess channels and asymmetrical junctions. The method includes forming an impurity region for adjusting the threshold voltage by implanting ions into a bit line junction of a semiconductor substr...	06/03/2008
7375004	Method of making an isolation trench and resulting isolation trench A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of t...	05/20/2008
7368800	Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ...	05/06/2008
7368366	Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ...	05/06/2008
7364975	Semiconductor device fabrication methods Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the ...	04/29/2008
7364981	Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ...	04/29/2008
7361546	Method of forming conductive stud on vertical memory device A method of forming a conductive stud is provided. The method includes providing a substrate which has an upper surface and an opening. The opening exposes a portion of a vertical memory device. A conductive layer is formed over the substrate to fill the opening. A ...	04/22/2008
7358566	Semiconductor device A first main electrode is provided on one surface thereof. On the other surface thereof, a second semiconductor layer of the first conduction type and a third semiconductor layer of the second conduction type are arranged alternately along the surface. A fourth semi...	04/15/2008
7358103	Method of fabricating an imaging device for collecting photons A photon collector has a reflecting metal layer to increase photon collection efficiency in a solid state imaging sensor. The reflecting metal layer reflects incident light internally to a photosensor. A plurality of photon collectors is formed in a wafer substrate ...	04/15/2008
7354818	Process for high voltage superjunction termination A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termin...	04/08/2008
7323379	Fabrication process for increased capacitance in an embedded DRAM memory An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capac...	01/29/2008
7314792	Method for fabricating transistor of semiconductor device A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to fo...	01/01/2008
7309640	Method of fabricating an integrated circuit including hollow isolating trenches and corresponding integrated circuit A method is provided for fabricating an integrated circuit. According to the method, hollow isolating trenches are produced within a substrate, and active components are produced in and on active areas of the substrate that are between the trenches. The trenches are...	12/18/2007
7294571	Concave pattern formation method and method for forming semiconductor device A pattern formation method includes the steps of forming a flowable film made of a material with flowability; forming at least one of a concave portion and a convex portion provided on a pressing face of a pressing member onto the flowable film by pressing the press...	11/13/2007
7282400	Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility of approxim...	10/16/2007
7276411	Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described...	10/02/2007
7276426	Methods of forming semiconductor constructions The invention includes a method of forming a semiconductor construction. A semiconductor substrate is placed within a reaction chamber. The substrate comprises a center region and an edge region surrounding the center region. The substrate comprises openings within ...	10/02/2007
7274084	Enhanced PFET using shear stress A semiconductor device structure includes a gate structure disposed on a portion of substrate, source and drain regions disposed adjacent to the portion so as to form a channel region in the portion, and trench isolation regions located immediately adjacent to the s...	09/25/2007
7271108	Multiple mask process with etch mask stack A method for forming etch features in an etch layer over a substrate is provided. An etch mask stack is formed over the etch layer. A first mask is formed over the etch mask stack. A sidewall layer is formed over the first mask, which reduces the widths of the space...	09/18/2007
7271107	Reduction of feature critical dimensions using multiple masks A method for forming features in an etch layer is provided. A first mask is formed over the etch layer wherein the first mask defines a plurality of spaces with widths. A sidewall layer is formed over the first mask. Features are etched into the etch layer through t...	09/18/2007
7268028	Well isolation trenches (WIT) for CMOS devices A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical ...	09/11/2007
7268057	Methods of filling openings with oxide, and methods of forming trenched isolation regions The invention includes methods in which oxide is formed within openings in a three-step process. A first step is deposition of oxide under a pressure of greater than 15 mTorr. A second step is removal of a portion of the oxide with an etch. A third step is an oxide ...	09/11/2007
7235459	Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ...	06/26/2007
7220640	Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation ...	05/22/2007
7166519	Method for isolating semiconductor devices with use of shallow trench isolation method The present invention relates to a method for isolating semiconductor devices. The method includes the steps of: forming a patterned pad nitride layer pattern to open at least one isolation region on the substrate; forming a first trench and a second trench by etchi...	01/23/2007
7144764	Method of manufacturing semiconductor device having trench isolation The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitri...	12/05/2006
6703287	Production method for shallow trench insulation An improved method for producing a semiconductor device in which overpolishing is prevented at a chemical mechanical polishing time to eliminate the influence of peripheries on the object part. A plasma oxide film is formed on a semiconductor substrate so...	03/09/2004

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Class 257/E21.548 - Concurrent filling of plurality of trenches having different trench shape or dimension, e.g., rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches (EPO)