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Class 257/E21.544 - PN junction isolation (EPO)


Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.54. This subclass
No. of patents: 405
Last issue date: 04/22/2008


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NumberTitleIssue Date
7361540Method of reducing noise disturbing a signal in an electronic device
Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing a second layer doped with a second dopant. A first signaling compone...
04/22/2008
7297607Device and method of performing a seasoning process for a semiconductor device manufacturing apparatus
A method of performing a seasoning process for a semiconductor device processing apparatus is provided by the present invention. The method includes: forming a material layer on a test wafer; coating a photoresist on the material layer; patterning the photoresist so...
11/20/2007
7189607Formation of standard voltage threshold and low voltage threshold MOSFET devices
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within...
03/13/2007
7095087Semiconductor device and fabrication method thereof
A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad ...
08/22/2006
6800916Implantable cardiac defibrillation with control circuit for controlling a high voltage circuit using a low voltage circuit
Disclosed is an implantable cardiac defibrillator (50) with a circuit comprising a capacitively coupled bridge circuit (10) for using a low-voltage circuit to operate a high-voltage circuit. The invention maintains isolation between the high- and low v...
10/05/2004
6693019METHOD OF MANUFACTURING AN ELECTRONIC POWER DEVICE MONOLITHICALLY INTEGRATED ON A SEMICONDUCTOR AND COMPRISING A FIRST POWER REGION, A SECOND REGION, AND AN ISOLATION STRUCTURE OF LIMITED PLANAR DIMENSION
An electronic power device is integrated monolithically in a semiconductor substrate. The device has a first power region and a second region, each region including P/N junction formed of a first semiconductor region with a first type of conductivity, whi...
02/17/2004
6689672Buried layer manufacturing method
A method of forming separate buried layers close to one another in a semiconductor component. This method includes the steps of forming, by implantation, doped areas in a semiconductor substrate; performing an anneal just sufficient to eliminate crystal d...
02/10/2004
6664608Back-biased MOS device
A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. T...
12/16/2003
6656803Radiation hardened semiconductor memory
A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure incl...
12/02/2003
6657274Apparatus for controlling a high voltage circuit using a low voltage circuit
Disclosed is a capacitively coupled bridge circuit for using a low-voltage circuit to operate a high-voltage circuit. The invention maintains isolation between the high- and low-voltage sections by using a capacitor. Also disclosed is the use of the inven...
12/02/2003
6657229Semiconductor device having multiple transistors sharing a common gate
A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, which may be of oppo...
12/02/2003
6645854Formation of a vertical junction throuph process simulation based optimization of implant doses and energies
A substantially vertical isolation junction between semiconductor devices is provided. The substantially vertical junction between a P-doped region and an N-doped region allows the P-doped region to be adjacent to the N-doped region with a lateral stagger...
11/11/2003
6639294Semiconductor device having a device formation region protected from a counterelectromotive force
A semiconductor device includes an epitaxial layer formed on a P type silicon substrate; a P+ diffusion layer for dividing the epitaxial layer into an N- epi layer, which constitutes a device formation region, and an N- epi layer, which constitutes an inv...
10/28/2003
6633073Method and apparatus for isolating circuits using deep substrate n-well
Techniques to isolate noise-sensitive circuits from noise generated by nearby circuits. In one design, a quiet region is formed on a die when surrounded by a deep n-well formed on top of a p-type substrate. The deep n-well is heavily doped n-type and form...
10/14/2003
6630700NMOS circuit in isolated wells that are connected by a bias stack having pluralirty of diode elements
An integrated NMOS circuit including an active stack having a plurality of isolated p-well active devices M1-M3, a bias stack having a plurality of diode-connected isolated p-well bias devices M4-M6, the gate of each of the plurality of diode-connected is...
10/07/2003
6628852Isolation device
An isolation device that can be used for providing optical and electrical isolation between areas of an integrated chip. The isolation device includes three doped elongate regions which form diodes which can be connected in series. The isolation device ca...
09/30/2003
6621327Substrate voltage selection circuit
Transistors are supplied with either a first power supply voltage or a second power supply voltage lower than the first power supply voltage. During an operation period of the transistors, substrate voltages of the transistors are set at a value between t...
09/16/2003
6607960Bipolar transistor manufacturing method
A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a seco...
08/19/2003
6605857Reducing magnetic coupling using triple well
An integrated inductive element may be formed over a substrate. A triple well may be defined in a star-shape, in one embodiment, in the substrate beneath the integrated inductive element in order to reduce eddy current losses arising from magnetic couplin...
08/12/2003
6605527Reduced area intersection between electrode and programming element
A method comprising forming a first dielectric layer over an electrode formed to a first contact point on a substrate, the electrode having a contact area; patterning the first dielectric layer into a body, a thickness of the first dielectric layer defini...
08/12/2003
6600199Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity
The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of...
07/29/2003
6596575High voltage breakdown isolation semiconductor device and manufacturing process for making the device
In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage elem...
07/22/2003
6589834Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current
The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated f...
07/08/2003
6583486Semiconductor memory device and its method of manufacture
A semiconductor memory device comprises a semiconductor substrate having a memory cell region and a periphery circuit region. The memory cell region includes first and second conductivity type wells and an array of memory cell formed on the first and seco...
06/24/2003
6583453Semiconductor device having a voltage-regulator device
A semiconductor device providing an improved effect of suppressing variation with time of reverse breakdown voltage applied to PN junction, particularly, a voltage-regulator device, is provided. The semiconductor device includes an impurity diffusion laye...
06/24/2003
6583487Power component bearing interconnections
A power component formed in an N-type silicon substrate delimited by a P-type wall, having a lower surface including a first P-type region connected to the wall, and an upper surface including a second P-type region, a conductive track extending above the...
06/24/2003
6583001Method for introducing an equivalent RC circuit in a MOS device using resistive paths
A method for providing low power MOS devices that include resistive paths specifically designed to provide a specified resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is in...
06/24/2003
6583473Semiconductor devices containing surface channel mos transistors
An intermediate semiconductor device for use in making surface channel MOS transistors is disclosed. The intermediate semiconductor device includes a semiconductor substrate having a top surface, a bottom surface, a plurality of doped isolation regions an...
06/24/2003
6583496Single-control monolithic component for a composite bridge
A monolithic component including two thyristors of a composite bridge connected to an A.C. voltage terminal by a common terminal corresponding to a common rear surface metallization forming an electrode of opposite biasing of each thyristor. An isolating ...
06/24/2003
6580142Electrical control methods involving semiconductor components
A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these ...
06/17/2003
6579782Vertical power component manufacturing method
A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant ...
06/17/2003
6573582Semiconductor device
A bipolar transistor is formed on a semiconductor substrate. A Schottky diode is formed in the collector region of the bipolar transistor. The collector region and the semiconductor substrate are isolated in potential from each other by potential isolatin...
06/03/2003
6573562Semiconductor component and method of operation
A semiconductor component includes a semiconductor substrate (110) having first and second portions (111, 112) with a first conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit (150, 350,...
06/03/2003
6573550Semiconductor with high-voltage components and low-voltage components on a shared die
A method and apparatus for increasing a breakdown voltage of a semiconductor device. The semiconductor device is constructed within an epitaxial tub of a first conductivity type formed within a dielectric material and comprises a surface diffusion region ...
06/03/2003
6566732High voltage resistive structure integrated on a semiconductor substrate
A resistive structure integrated on a semiconductive substrate is described. The resistive structure has a first type of conductivity formed into a serpentine region of conductivity which is opposite to that of the semiconductive substrate. In at least tw...
05/20/2003
6563181High frequency signal isolation in a semiconductor device
A semiconductor device (20) includes an isolated p-well (22) formed in a substrate (21) by a buried n-well (25) and an n-well ring (24). The n-well ring (24) extends from a surface of the semiconductor device (20) to the buried n-well (25). The isolated p...
05/13/2003
6559515Insulating wall between power components
An insulating wall of a second conductivity type intended for separating elementary components formed in different wells of a semiconductive layer of a first conductivity type, a component located in one at least one of the wells being capable of operatin...
05/06/2003
6555857Semiconductor device
The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substr...
04/29/2003
6555893Bar circuit for an integrated circuit
The present invention provides a bar circuit for reducing cross talk and eddy current of an integrated circuit. The bar circuit comprises a semiconductor substrate with a first conductivity type; a strip of first well with a second conductivity type in th...
04/29/2003
6551868Vertical power component manufacturing method
A method for manufacturing a vertical power component on a silicon wafer, including the steps of growing a lightly-doped epitaxial layer of a second conductivity type on the upper surface of a heavily-doped substrate of a first conductivity type, the epit...
04/22/2003
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