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| Number | Title | Issue Date |
| 6855606 | Semiconductor nano-rod devices In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of th... | 02/15/2005 |
| 6686616 | Silicon carbide metal-semiconductor field effect transistors SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two re... | 02/03/2004 |
| 6642559 | Structure and process for improving high frequency isolation in semiconductor substrates An isolation structure for high frequency integrated circuits is a conductive material disposed over a region of active gallium arsenide substrate. The conductive material over the active region creates a lossy RF path to reduce undesired coupling between... | 11/04/2003 |
| 6495407 | Method of making an article comprising an oxide layer on a GaAs-based semiconductor body A novel method of forming a GaAs-based MOS structure comprises ion implantation after oxide formation, and subsequent slow heating and cooling, carried out such that essentially no interfacial defects that are detectable by high resolution transmission el... | 12/17/2002 |
| 6472718 | Semiconductor device A semiconductor device includes an electrically conductive III-V doped semiconductor substrate of a first conduction type, a photodiode array having photodiode structures disposed on the III-V doped semiconductor substrate, a first III-V doped semiconduct... | 10/29/2002 |
| 6465270 | Process for producing a semiconductor device A semiconductor device includes an electrically conductive III-V doped semiconductor substrate of a first conduction type, a photodiode array having photodiode structures disposed on the III-V doped semiconductor substrate, a first III-V doped semiconduct... | 10/15/2002 |
| 6339233 | Metal clad ridge waveguide ("MCRW") laser semiconductor structure with doped semiconductor substrate A semiconductor device comprises an electrically conductive III-V semiconductor substrate which has mutually opposite first and second main surfaces. At least one pn junction, reverse biased during operation of the semiconductor device, is disposed above ... | 01/15/2002 |
| 6291277 | Method of manufacturing a semiconductor device including etching of a stack of layers by means of photolithography The invention relates to a method of manufacturing an integrated semiconductor device on a substrate (1), comprising steps to manufacture a stack of layers (2, 3, 4, 5) on the substrate, and steps to manufacture circuit elements by means of photolithograp... | 09/18/2001 |
| 6235617 | Semiconductor device and its manufacturing method It is intended to provide a semiconductor device and its manufacturing method in which a high-resistance region maintaining a high resistance even under high temperatures can be made in a nitride III-V compound semiconductor layer having an electric condu... | 05/22/2001 |
| 6111273 | Semiconductor device and its manufacturing method It is intended to provide a semiconductor device and its manufacturing method in which a high-resistance region maintaining a high resistance even under high temperatures can be made in a nitride III-V compound semiconductor layer having an electric condu... | 08/29/2000 |
| 6100548 | Modulation-doped field-effect transistors and fabrication processes A process is provided for fabricating MODFET's in group III nitride compound semiconductors. The process precedes isolation of the MODFET structure with the use of e-beam lithography to define very narrow (e.g., ~0.25 micrometer) gates which enhance trans... | 08/08/2000 |
| 5982023 | Semiconductor device and field effect transistor A dummy gate is removed together with an SiO2 film thereon by lift-off to form a reverse dummy-gate pattern with the SiO2 film. A photoresist pattern is formed to cover the reverse dummy-gate pattern and an SiN protection film thereb... | 11/09/1999 |
| 5943577 | Method of making heterojunction bipolar structure having air and implanted isolations In a method manufacturing a semiconductor device, a semiconductor layer having a device forming region is formed on substrate. Next, a region except for the device forming region is changed into an insulator. In this case, a conducting path is left across... | 08/24/1999 |
| 5942772 | Semiconductor device and method of manufacturing the same A heterojunction epitaxial layer, including a first semiconductor layer containing Al and having a thickness of 50 nm or less and a second semiconductor layer different in composition from the first semiconductor layer, is formed on a substrate composed o... | 08/24/1999 |
| 5940694 | Field effect transistor process with semiconductor mask, single layer integrated metal, and dual etch stops A method for fabricating a periodic table group III-IV field-effect transistor device is described. The disclosed fabrication arrangement uses a single metallization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch ... | 08/17/1999 |
| 5939739 | Separation of thermal and electrical paths in flip chip ballasted power heterojunction bipolar transistors The present invention relates to a heterojunction bipolar transistor structure having a device mesa 401 with a collector region 402, a base region 403 and an emitter region 404. An emitter metal layer 405 is connected to a ballast resistor 406 which in tu... | 08/17/1999 |
| 5888890 | Method of manufacturing field effect transistor A method of manufacturing a field effect transistor according to the present invention is disclosed including the steps of preparing a semiconductor substrate; forming an insulating film for use as high concentration on the semiconductor substrate; formin... | 03/30/1999 |
| 5856217 | Modulation-doped field-effect transistors and fabrication processes A process is provided for fabricating MODFET's in group III nitride compound semiconductors. The process precedes isolation of the MODFET structure with the use of e-beam lithography to define very narrow (e.g., ~0.25 micrometer) gates which enhance trans... | 01/05/1999 |
| 5854086 | Method for manufacturing planar field effect transistors and planar high electron mobility transistors An apparatus and method of processing a planar HEMT or FET semiconductor device is disclosed. An ohmic metalization is patterned on a semiconductor surface then lifted-off. A plurality of process control monitors are isolated, preferably using a wet etch ... | 12/29/1998 |
| 5844303 | Semiconductor device having improved electronic isolation A semiconductor device includes a buffer layer of AlGaAs that contains oxygen with a concentration level in the approximate range of 8×1017 cm-3 to 6×1019 cm-3, and carbon with a concentration level in the app... | 12/01/1998 |
| 5796131 | Metal semiconductor field effect transistor (MESFET) device with single layer integrated metal A periodic table group III-IV metal semiconductor metal field-effect transistor device is described. The disclosed device includes single metalization for ohmic and Schottky barrier contacts, an elective permanent etch stop layer, a non-alloyed ohmic cont... | 08/18/1998 |
| 5786261 | Method for fabricating semiconductor device having device isolation layer First, a non-doped AlGaAs layer and an n-GaAs layer serving as a conductive layer are formed in order on the surface of a semi-insulating GaAs substrate. Then, a photoresist film having an opening in its predetermined position is formed on the surface of ... | 07/28/1998 |
| 5760418 | GaAs power semiconductor device operating at a low voltage and method for fabricating the same Disclosed is a GaAs power semiconductor device operating at a low voltage and a method for fabricating the device, the method comprising the steps of sequentially forming a first undoped GaAs buffer layer, a superlattice layer, a second undoped GaAs buffe... | 06/02/1998 |
| 5725786 | Durable mask and method of fabrication The durable mask includes a polyimide layer formed over a portion of a semiconductor substrate to be masked. A heavy metal layer is then formed over the polyimide layer. An adhesion layer is formed between the polyimide layer and the heavy metal layer to ... | 03/10/1998 |
| 5726462 | Semiconductor structures having electrically insulating and conducting portions formed from an AlSb-alloy layer A semiconductor structure. The semiconductor structure comprises a plurality of semiconductor layers formed on a substrate including at least one layer of a III-V compound semiconductor alloy comprising aluminum (Al) and antimony (Sb), with at least a par... | 03/10/1998 |
| 5702975 | Method for isolating semiconductor device A method for isolating a semiconductor device is disclosed including the steps of sequentially growing a plurality of material layers on a semiconductor substrate, etching the material layers down to a predetermined depth of the substrate to thereby defin... | 12/30/1997 |
| 5698900 | Field effect transistor device with single layer integrated metal and retained semiconductor masking A periodic table group III-IV field-effect transistor device is described. The disclosed device uses a single metalization for ohmic and Schottky barrier contacts, permanent plural etch stop layers, employs a non-alloyed ohmic connection semiconductor lay... | 12/16/1997 |
| 5684819 | Monolithically integrated circuits having dielectrically isolated, electrically controlled optical devices A fabrication technique for improved dielectric isolation of adjacent, electronic devices or electrically controllable optical devices provides an inter-device resistance in excess of 1 MΩ. Strips of a silicon oxide material, such as SiO2, are... | 11/04/1997 |
| 5677230 | Method of making wide bandgap semiconductor devices A method of planarizing wide bandgap semiconductor devices selected from a group including SiC, GaN and diamond having a mesa defined thereon by a trench with a depth of 1 to 2 micrometers and a width of 2 to 10 micrometers. A layer of dielectric material... | 10/14/1997 |
| 5677554 | FET having a dielectrically isolated gate connect A HIGFET having a gate with a pad which is isolated from the FET heterostructure wafer by a dielectric layer to minimize leakage current between the gate and the wafer. The method of production of this device involves application of the gate metal only ov... | 10/14/1997 |
| 5640026 | Compound semiconductor device including implanted isolation regions A method of performing element separation by ion implantation for a compound semiconductor device includes performing first ion implantation into the entire contour of the device periphery region to produce a first insulating region having a region of the... | 06/17/1997 |
| 5639677 | Method of making a gaAs power semiconductor device operating at a low voltage Disclosed is a GaAs power semiconductor device operating at a low voltage and a method for fabricating the device, the method comprising the steps of sequentially forming a first undoped GaAs buffer layer, a superlattice layer, a second undoped GaAs buffe... | 06/17/1997 |
| 5633183 | FET having minimized parasitic gate capacitance A HIGFET having a gate pad situated over a non conducting portion of the channel layer of the heterostructure wafer. The method of producing this device involves application of a very thin layer of gate metal on the wafer to protect the wafer surface duri... | 05/27/1997 |
| 5610095 | Monolithically integrated circuits having dielectrically isolated, electrically controlled optical devices and process for fabricating the same A fabrication technique for improved dielectric isolation of adjacent, electronic devices or electrically controllable optical devices provides an inter-device resistance in excess of 1 MΩ. Strips of a silicon oxide material, such as SiO2, are... | 03/11/1997 |
| 5593917 | Method of making semiconductor components with electrochemical recovery of the substrate The method is characterized by the steps consisting in: a) producing a semi-insulating or n-type substrate; b) forming a separating layer of a p+ -type doped material on the surface of said substrate; c) forming an active layer on said separati... | 01/14/1997 |
| 5569953 | Semiconductor device having an isolation region enriched in oxygen A method for growing an epitaxial layer of a group III-V compound semiconductor material that contains oxygen comprises the steps of supplying molecules of an organic compound that contains a group V element and oxygen in the molecule, and decomposing the... | 10/29/1996 |
| 5508210 | Element isolating method for compound semiconductor device A method of element isolation includes implanting ions in a compound semiconductor substrate at the periphery of a semiconductor device in the substrate to produce a first insulating region having a region of maximum implanted ion concentration within a b... | 04/16/1996 |
| 5483089 | Electrically isolated MESFET An electrically isolated MESFET includes a compound semiconductor substrate; a plurality of compound semiconductor layers disposed on the compound semiconductor substrate; a MESFET structure in a prescribed region of the compound semiconductor layers; an ... | 01/09/1996 |
| 5482872 | Method of forming isolation region in a compound semiconductor substrate Compound semiconductor devices (10, 11) having isolation regions (37) under gate pads (24, 27) and a method of forming the compound semiconductor devices (10, 11). A surface protection layer (33) is formed on a compound semiconductor substrate (31). The s... | 01/09/1996 |
| 5480833 | Semiconductor device having an isolation region enriched in oxygen and a fabrication process thereof A method for growing an epitaxial layer of a group III-V compound semiconductor material that contains oxygen comprises the steps of supplying molecules of an organic compound that contains a group V element and oxygen in the molecule, and decomposing the... | 01/02/1996 |
