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| Number | Title | Issue Date |
| 7439580 | Top drain MOSgated device and process of manufacture therefor A trench type top drain MOSgated device has a drain electrode on the die top and a source electrode on the die bottom surface. The device is turned on by a control voltage connected between a drain and a gate region. The device cell has a body short trench and a gat... | 10/21/2008 |
| 7413981 | Pitch doubled circuit layout In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry includes providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other... | 08/19/2008 |
| 7410892 | Methods of fabricating integrated circuit devices having self-aligned contact structures An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first in... | 08/12/2008 |
| 7375019 | Image sensor and method for fabricating the same An image sensor and a method for fabricating the same are disclosed, to improve a contact quality between a contact plug and a source diffusion layer. The image sensor includes a photodiode in an active area of a semiconductor substrate, for receiving incident exter... | 05/20/2008 |
| 7348263 | Manufacturing method for electronic component, electronic component, and electronic equipment A manufacturing method for electronic device, includes: preparing a first substrate having a plurality of first regions; preparing a second substrate having a plurality of second regions; facing the first region and the second region each other, and connecting the f... | 03/25/2008 |
| 7339830 | One transistor SOI non-volatile random access memory cell Various semiconductor structure embodiments include a substrate, a buried insulator over at least a portion of the substrate, a body region over the buried insulator, first and second source/drain regions to provide a channel region in the body region, a gate insula... | 03/04/2008 |
| 7332401 | Method of fabricating an electrode structure for use in an integrated circuit An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the d... | 02/19/2008 |
| 7323389 | Method of forming a FINFET structure A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gat... | 01/29/2008 |
| 7202155 | Method for manufacturing wiring and method for manufacturing semiconductor device The present invention provides a method for manufacturing a wiring and a method for manufacturing a semiconductor device, which do not require a photolithography step in connecting a pattern of an upper layer and a pattern of a lower layer. According to the present ... | 04/10/2007 |
| 7122463 | Manufacturing method of semiconductor device When the occurrence of the bowing is controlled through the etching conditions, a change in etching conditions causes the bowing. Another problem is a requirement of the larger-sized apparatus for the substrate with a larger diameter in order to allow a whole substr... | 10/17/2006 |
| 6677644 | Semiconductor integrated circuit having low voltage and high voltage transistors An integrated circuit formed on a SOI substrate has a low withstand voltage MOS transistors formed in the SOI substrate and comprising source and drain regions formed in the semiconductor film of the SOI substrate, a gate insulating film formed over the s... | 01/13/2004 |
| 6670716 | Silicon-on-insulator (SOI) semiconductor structure for implementing transistor source connections using buried dual rail distribution Silicon-on-insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rail distribution. A SOI semiconductor structure includes a SOI transistor having a silicide layer... | 12/30/2003 |
| 6667202 | Semiconductor device and method for making the same A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the su... | 12/23/2003 |
| 6664150 | Active well schemes for SOI technology A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes ... | 12/16/2003 |
| 6642148 | RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The se... | 11/04/2003 |
| 6632710 | Method for forming semiconductor device In a method for forming a silicon-on-insulator FET having a contact that provides a fixed potential to a substrate, the substrate-biasing between the SOI transistor and the silicon substrate is performed via a plug. As a result, a contact hole for the sub... | 10/14/2003 |
| 6627484 | Method of forming a buried interconnect on a semiconductor on insulator wafer and a device including a buried interconnect A buried interconnect can be incorporated into the starting semiconductor on insulator wafer during the early stages of the circuit fabrication process flow for use with semiconductor devices. The buried interconnect provides an additional interconnect la... | 09/30/2003 |
| 6624497 | Semiconductor device with a reduced mask count buried layer An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of dif... | 09/23/2003 |
| 6620663 | Self-aligned copper plating/CMP process for RF lateral MOS device A method of fabricating an RF lateral MOS device, comprising the following steps. A substrate having a gate oxide layer formed thereover is provided. A first layer of polysilicon is formed over the gate oxide layer. A second layer of material is formed ov... | 09/16/2003 |
| 6620694 | Method of making non volatile memory with a protective metal line A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over t... | 09/16/2003 |
| 6607959 | Integrated circuit devices having trench isolation structures and methods of fabricating the same Integrated circuit devices include an integrated circuit substrate having a face and a trench in the face. The trench has a trench sidewall and a trench floor. A first insulating layer is provided on the trench sidewall that exposes at least part of the t... | 08/19/2003 |
| 6603166 | Frontside contact on silicon-on-insulator substrate A method of forming a frontside contact to a Silicon-On-Insulator (SOI) wafer is described. A connection polysilicon connects a silicon substrate layer to a contact plug. This connection provides a means to ground or bias the bottom substrate of the SOI w... | 08/05/2003 |
| 6576508 | Formation of a frontside contact on silicon-on-insulator substrate A method of forming a frontside contact to a Silicon-On-Insulator (SOI) wafer is described. A connection polysilicon connects a silicon substrate layer to a contact plug. This connection provides a means to ground or bias the bottom substrate of the SOI w... | 06/10/2003 |
| 6528847 | Metal oxide semiconductor device having contoured channel region and elevated source and drain regions A metal oxide semiconductor (MOS) device includes a silicon substrate, source and drain regions having a predetermined junction depth (dj) relative to the surface of the silicon substrate, and a gate region having a contoured channel region for... | 03/04/2003 |
| 6528840 | Semiconductor device A semiconductor device in which polysilicon is used to form source and drain regions in an initial process step so as to reduce resistance of bit lines and minimize a junction capacitance and thus improve its reliability, and a method for fabricating the ... | 03/04/2003 |
| 6521947 | Method of integrating substrate contact on SOI wafers with STI process A method for forming a substrate contact in a substrate that includes a silicon on insulator region. A shallow isolation trench is formed in the silicon on insulator substrate. The shallow isolation trench is filled. Photoresist is deposited on the substr... | 02/18/2003 |
| 6521923 | Microwave field effect transistor structure on silicon carbide substrate A microwave transistor structure comprising: (a) a SiC substrate having a top surface; (b) a silicon semiconductor material of a first conductivity type overlaying the top surface of the semiconductor substrate and having a top surface; (c) a conductive g... | 02/18/2003 |
| 6498057 | Method for implementing SOI transistor source connections using buried dual rail distribution Methods and silicon-on-Insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rall distribution. A SOI semiconductor structure Includes a SOI transistor having a si... | 12/24/2002 |
| 6492676 | Semiconductor device having gate electrode in which depletion layer can be generated A semiconductor device including a first gate electrode having a first plane provided opposite to a first semiconductor region where a channel is to be formed with a first gate insulation film interposed therebetween; a second gate insulation film includi... | 12/10/2002 |
| 6492684 | Silicon-on-insulator chip having an isolation barrier for reliability An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above ... | 12/10/2002 |
| 6469350 | Active well schemes for SOI technology A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes ... | 10/22/2002 |
| 6451633 | Method for manufacturing semiconductor integrated circuit A semiconductor integrated circuit is manufactured by forming an insulation film on a semiconductor substrate, forming an SOI film on the insulation film, forming an oxide film on the SOI film, and forming a contact hole penetrating through the oxide film... | 09/17/2002 |
| 6441435 | SOI device with wrap-around contact to underside of body, and method of making A transistor device on an SOI wafer includes a metal connect that is in contact with an underside (a bottom surface) of a body of the device. A part of the metal connect is between an active semiconductor region of the device and an underlying buried insu... | 08/27/2002 |
| 6436744 | Method and structure for creating high density buried contact for use with SOI processes for high performance logic A semiconductor device having an SOI FET comprising a silicon body on an insulating layer on a conductive substrate. A gate dielectric and a gate are provided on a surface of the silicon body, and a source and a drain are provided on two sides of the gate... | 08/20/2002 |
| 6429099 | Implementing contacts for bodies of semiconductor-on-insulator transistors A method and semiconductor structure are provided for implementing body contacts for semiconductor-on-insulator transistors. A bulk semiconductor substrate is provided. A mask is applied to the bulk semiconductor substrate to block an insulating implant l... | 08/06/2002 |
| 6410384 | Method of making an electric conductive strip A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of a trench. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sen... | 06/25/2002 |
| 6399436 | Method of making an electric conductive strip A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of the barrier, a vertical surface and a lower horizontal surface. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. N... | 06/04/2002 |
| 6399987 | MOS transistor having self-aligned well bias area A MOS transistor having a self-aligned well bias area and a method of fabricating the same provide for efficient application of well bias in a highly integrated semiconductor substrate without causing latch-up. The well bias area is formed at a trench, wh... | 06/04/2002 |
| 6372562 | Method of producing a semiconductor device A method of producing a semiconductor device forming a transistor on a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer, including the steps of forming an element isolation region connected to the first s... | 04/16/2002 |
| 6358782 | Method of fabricating a semiconductor device having a silicon-on-insulator substrate and an independent metal electrode connected to the support substrate A plurality of semiconductor components (33, 35) isolated by an insulating film (39) are formed on a buried oxidation film (3) of an SOI substrate (1), substrate contact holes (5, 6) through the insulating film (39) and the buried oxidation film (3) are p... | 03/19/2002 |
