Class 257/E21.507 - Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.506. This subclass
No. of patents: 951
Last issue date: 10/28/2008

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Number	Title	Issue Date
7442635	Method for producing a semiconductor device and resulting device The present invention is related to a method of producing a semiconductor device and the resulting device. The method is suitable in the first place for producing high power devices, such as High Electron Mobility Transistors (HEMT), in particular HEMT-devices with ...	10/28/2008
7435621	Method of fabricating wafer level package A method of fabricating wafer level package is provided. First, a wafer having a front and a rear surfaces is provided. Several fosses are then formed on the front surface of the wafer. Next, an insulative layer is formed on a surface of each fosse; a conductive lay...	10/14/2008
7427544	Semiconductor device and method of manufacturing the same A semiconductor device includes an element isolation insulating film provided in a semiconductor substrate between first and second element regions, a gate electrode running over the element isolation insulating film, first and second element regions, a first stoppe...	09/23/2008
7422942	Method for fabricating a semiconductor device having an insulation film with reduced water content A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the ...	09/09/2008
7419878	Planarized and silicided trench contact Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures i...	09/02/2008
7413972	Method of forming a metal interconnection line in a semiconductor device using an FSG layer A method of forming a metal line in a semiconductor device using a fluorine doped silica glass (FSG) insulation layer. The method includes forming a lower metal layer on a insulation layer on a semiconductor substrate, forming a metal oxide layer on a sidewall of th...	08/19/2008
7410892	Methods of fabricating integrated circuit devices having self-aligned contact structures An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first in...	08/12/2008
7411240	Integrated circuits including spacers that extend beneath a conductive line Integrated circuit devices are fabricated by fabricating a conductive line on an insulating layer on an integrated circuit substrate. The conductive line includes a bottom adjacent the insulating layer, a top remote from the insulating layer and first and second sid...	08/12/2008
7397130	Semiconductor devices with contact holes self-aligned in two directions A method of forming a semiconductor device can include forming a plurality of gate structure patterns including gates and first mask patterns stacked on a semiconductor substrate, the gate structure patterns being spaced apart from each other and extending in a firs...	07/08/2008
7396751	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes forming a second storage node contact hole with a mask for storage node and securing an overlay margin between a storage node contact hole and a storage node with a hard mask layer that serves as a hard mask...	07/08/2008
7397073	Barrier dielectric stack for seam protection The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal ...	07/08/2008
7390737	Method for filling a contact hole and integrated circuit arrangement with contact hole A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting ...	06/24/2008
7381612	Method for manufacturing semiconductor device with recess channels and asymmetrical junctions Disclosed is a method for manufacturing a semiconductor device having recess channels and asymmetrical junctions. The method includes forming an impurity region for adjusting the threshold voltage by implanting ions into a bit line junction of a semiconductor substr...	06/03/2008
7374967	Multi-stack chip size packaging method In multi-stack chip size packaging a plurality chips, a first chip is electrically interconnected on a top surface of a substrate using a bump. Next, an epoxy is coated on the first chip and is stacked a second chip thereon, wherein the second chip is electrically i...	05/20/2008
7364957	Method and apparatus for semiconductor device with improved source/drain junctions A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrat...	04/29/2008
7358188	Method of forming conductive metal silicides by reaction of metal with silicon The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a ni...	04/15/2008
7341920	Method for forming a bipolar transistor device with self-aligned raised extrinsic base Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-art lithographi...	03/11/2008
7338867	Semiconductor device having contact pads and method for manufacturing the same Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. S...	03/04/2008
7335536	Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps loc...	02/26/2008
7316958	Masks for fabricating semiconductor devices and methods of forming mask patterns Masks for fabricating a semiconductor device and methods of forming mask patterns are provided which are capable of enhancing the breakdown voltage of the fabricated semiconductor device by accurately correcting a line width pattern error of a semiconductor substrat...	01/08/2008
7312164	Selective passivation of exposed silicon A method for applying a passivation layer selectively on an exposed silicon surface includes use of a liquid phase solution supersaturated in silicon dioxide. The application is conducted at substantially atmospheric temperature and pressure and achieves an effectiv...	12/25/2007
7282418	Method for fabricating a self-aligned bipolar transistor without spacers According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated o...	10/16/2007
7276409	Method of forming a capacitor A carbon containing masking layer is patterned to include a plurality of container openings therein having minimum feature dimensions of less than or equal to 0.20 micron. The container openings respectively have at least three peripheral corner areas which are each...	10/02/2007
7265405	Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines....	09/04/2007
7259083	Local interconnect manufacturing process The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The fi...	08/21/2007
7247517	Method and apparatus for a dual substrate package A semiconductor die having a through via formed therein is disclosed. A first conductive layer is formed on the front side of the die and a second conductive layer is formed on the backside of the die, and coupled with the through via. A first package substrate is e...	07/24/2007
7232720	Method for fabricating a semiconductor device having an insulation film with reduced water content A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the ...	06/19/2007
7220653	Plasma display panel and manufacturing method thereof A manufacturing method of a plasma display panel and the plasma display panel made using the manufacturing method include the align marks being maintained in a discernible state. The method for manufacturing a plasma display panel includes forming electrodes on a su...	05/22/2007
7192859	Method of manufacturing semiconductor device and display device To provide a method of forming a wiring for the purpose of providing a semiconductor device, which is superior in reliability and cost performance. Further, to provide methods of manufacturing a semiconductor device and a display device by using the method of formin...	03/20/2007
7169676	Semiconductor devices and methods for forming the same including contacting gate to source Semiconductors having electrically coupled gate and impurity doped regions and methods for fabricating the same are provided. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and an impurity doped re...	01/30/2007
7148108	Method of manufacturing semiconductor device having step gate Disclosed herein is a method of manufacturing a semiconductor device having a step gate, which can improve the refresh characteristics of the device. The method comprises the steps of: forming on a silicon substrate having active and field regions a first hard mask ...	12/12/2006
7138340	Method for fabricating semiconductor device without damaging hard mask during contact formation process Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer...	11/21/2006
7129113	Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture A method of making a three-dimensional stacked semiconductor package includes providing a first semiconductor chip assembly that includes a first chip, a first conductive trace and a first encapsulant, wherein the first conductive trace includes a first metal pillar...	10/31/2006
7129155	Process for producing a plurality of gate stacks which are approximately the same height and equidistant on a semiconductor substrate Process for producing a plurality of gate stacks approximately the same height and equidistant on a semiconductor substrate. The process includes providing a gate dielectric on the semiconductor substrate and applying and patterning at least a first layer and a seco...	10/31/2006
6769303	Multi-functional micro electromechanical silicon carbide accelerometer A method of bulk manufacturing SiC sensors is disclosed and claimed. Materials other than SiC may be used as the substrate material. Sensors requiring that the SiC substrate be pierced are also disclosed and claimed. A process flow reversal is employed whereby the m...	08/03/2004
6703314	Method for fabricating semiconductor device Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive p...	03/09/2004
6703305	Semiconductor device having metallized interconnect structure and method of fabrication A semiconductor device having a metallized interconnect structure includes a conductor having an upper contact surface and an edge surface depending from the upper contact surface. An opening in an insulating layer overlying the conduct exposes at least a...	03/09/2004
6703715	Semiconductor device having interconnection layer with multiply layered sidewall insulation film The semiconductor device comprises an interconnection layer 14 formed on a substrate 10, a cap insulation film 22 formed on the upper surface of the interconnection layer 14, and a sidewall insulation film which is formed on the side walls of the intercon...	03/09/2004
6703657	DRAM cell having electrode with protection layer A DRAM cell is provided, along with a method for fabricating such a DRAM cell. A protection layer pattern is formed to cover a common drain region of first and second access transistors. Storage node holes are then formed to expose each source region of t...	03/09/2004
6699793	Semiconductor device having multi-layered spacer and method of manufacturing the same A semiconductor device having a multi-layered spacer and a method of manufacturing the semiconductor device include gate electrodes each comprising a gate oxide layer, a gate conductive layer, and a capping dielectric layer formed on a semiconductor subst...	03/02/2004

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Class 257/E21.507 - Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)