Class 257/E21.45 - With Schottky gate, e.g., MESFET (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.4. This subclass
No. of patents: 45
Last issue date: 08/26/2008

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Number	Title	Issue Date
7416929	Monolithic vertical junction field effect transistor and schottky barrier diode fabricated from silicon carbide and method for fabricating the same A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device l...	08/26/2008
7307329	Electronic device with guard ring An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the substrate, an active layer arranged within the opening on the surface of the substrate, the active layer...	12/11/2007
6605519	Method for thin film lift-off processes using lateral extended etching masks and device A method for forming an etching mask structure on a substrate includes etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotr...	08/12/2003
6541319	Method of manufacturing a self-aligned gate transistor with P-type impurities selectively implanted below the gate, source and drain electrodes The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channe...	04/01/2003
6534822	Silicon on insulator field effect transistor with a double Schottky gate structure A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with an impurity to increase free carrier conductivity. The source r...	03/18/2003
6518129	Manufacture of trench-gate semiconductor devices The manufacture of a trench-gate semiconductor device, for example a power transistor or a memory device includes the steps of forming at a surface (10a) of a semiconductor body (10) a first mask (51) having a first window (51a), providing a thin layer of...	02/11/2003
6498071	Manufacture of trench-gate semiconductor devices In the manufacture of a trench-gate semiconductor device, for example a MOSFET or an IGBT, a starting semiconductor body (10) has two top layers (13, 15) provided for forming the source and body regions. Gate material (11') is provided in a trench (20) wi...	12/24/2002
6429457	Field-effect transistor A field-effect transistor is made with electrodes (2, 4, 5) and isolators (3) in vertically provided layers, such that at least the electrodes (4, 5) and the isolators (3) form a step (6) oriented vertically relative to the first electrode (2) or the subs...	08/06/2002
6117713	Method of producing a MESFET semiconductor device having a recessed gate structure An insulating layer is formed on a semiconductor substrate, and a first resist layer having a first resist opening portion is formed on the insulating layer. Then, the insulating layer is etched thought the opening portion to expose the substrate. After r...	09/12/2000
6060734	MESfield effect transistor In the manufacture of a field effect transistor which can improve the breakdown voltage between a gate and a drain and can also prevent a gate lag, an oxide film is formed or wet cleaning is carried out over the semiconductor surface of an inter-source-ga...	05/09/2000
5891769	Method for forming a semiconductor device having a heteroepitaxial layer A method for forming a relaxed semiconductor layer (12) includes forming a strained semiconductor layer on a substrate (11). The strained semiconductor layer has a different lattice constant than the substrate (11). Without exposing the strained semicondu...	04/06/1999
5599724	FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same An N-type source (or drain) region is formed in the surface area of a P-type silicon substrate. A first insulation film is formed on the silicon substrate and a gate electrode is formed on the first insulation film. A second insulation film is formed on t...	02/04/1997
5244832	Method for fabricating a poly emitter logic array and apparatus produced thereby A Schottky diode includes a metal layer (62) on an epitaxial region (24). The metal layer (62) is covered with a dielectric layer (64). An area (90) on the metal is exposed by opening a via (68) in the dielectric. The exposed area (90) is spaced from a bu...	09/14/1993
5140387	Semiconductor device in which gate region is precisely aligned with source and drain regions An aligned metal gate is formed on a semiconductor substrate surface between a source region and a drain region of the substrate. Precise alignment of the boundaries of the gate with the boundaries of the source and drain regions is obtained by shadowing ...	08/18/1992
5107312	Method of isolating a top gate of a MESFET and the resulting device A MESFET including a Schottky top gate which extends across the channel region between the source and drain regions and beyond two opposed sides of the dielectric isolation onto the substrate in which the device is built. The portion of the top gate which...	04/21/1992
5075746	Thin film field effect transistor and a method of manufacturing the same A thin film field effect transistor comprising a source electrode and a drain electrode joined to a first semiconductor layer respectively through first and second portions of a second doped semiconductor layer, a gate insulating layer, and a gate electro...	12/24/1991
4929568	Method of isolating a top gate of a MESFET and the resulting device A MESFET including a Schottky top gate which extends across the channel region between the source and drain regions and beyond two opposed sides of the dielectric isolation onto the substrate in which the device is built. The portion of the top gate which...	05/29/1990
4898838	Method for fabricating a poly emitter logic array A Schottky diode includes a metal layer (62) on an epitaxial region (24). The metal layer (62) is covered with a dielectric layer (64). An area (90) on the metal is exposed by opening a via (68) in the dielectric. The exposed area (90) is spaced from a bu...	02/06/1990
4847212	Self-aligned gate FET process using undercut etch mask The provision of an intermediately doped transition region between respective n+ implanted source and drain regions in a GaAs FET and the lightly doped channel region under the gate permits device optimizaiton for low source and drain resistance in EFET's...	07/11/1989
4838201	Apparatus and process for vacuum chemical epitaxy A vacuum chemical epitaxy apparatus comprising a first mixing chamber having an inlet for introducing a metal-organic gaseous materials and n-type and p-type dopants, and a plurality of outlets for directing the flow of said metal-organic gases and n-type...	06/13/1989
4821094	Gate alignment procedure in fabricating semiconductor devices A self-aligned metal gate is formed on a semiconductor substrate surface between a source region and a drain region of the substrate. Precise alignment of the boundaries of the gate with the boundaries of the source and drain regions is obtained by shadow...	04/11/1989
4745083	Method of making a fast IGFET An integrated circuit including CMOS transistors and an EPROM device by a method including selectively implanting threshold adjusting atoms of P-type in the channel regions of the N-type transistors while exposing the whole device area of the P-channel tr...	05/17/1988
4724223	Method of making electrical contacts Electrical contacts are made to conductive elements of an array which are embedded in a matrix of silicon with the conductive elements exposed at a surface. The surface is covered with silicon oxide, and an opening is made in the silicon oxide to expose a...	02/09/1988
4481704	Method of making an improved MESFET semiconductor device An improved MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a self-aligned gate process which consists of an implanted channel stopper underneath ...	11/13/1984
4466174	Method for fabricating MESFET device using a double LOCOS process MESFET devices are fabricated on a semiconductor substrate using a LOCOS (localized oxidation of silicon) process twice during the fabrication. The first LOCOS process provides device separation with a self-aligned thick-field oxide (SATO). The second LOC...	08/21/1984
4455738	Self-aligned gate method for making MESFET semiconductor A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/...	06/26/1984
4425379	Polycrystalline silicon Schottky diode array A process and structure are disclosed which are suitable for forming large arrays of Schottky diodes at desired locations between mutually perpendicular strips of aluminum and strips of metal-silicide. The invention is particularly useful in creating read...	01/10/1984
4407004	Self-aligned MESFET having reduced series resistance Disclosed herein is a structure and process for a self-aligned metal semiconductor field effect transistor having the characteristics of a high speed, high density, low power LSI circuit and specifically an improved high device gain MESFET device using co...	09/27/1983
4402128	Method of forming closely spaced lines or contacts in semiconductor devices A method for forming closely spaced conductors suitable for use, for example, in CCD's and MESFET's is described utilizing an edge diffusion technique to convert exposed edge portions of a polycrystalline silicon layer to a non-etchable form. The converte...	09/06/1983
4358891	Method of forming a metal semiconductor field effect transistor A metal silicon field effect transistor and the method of producing such a transistor whereby all of the elements of the transistor are defined by a single masking step. These elements include the channel of the first effect transistor as well as the sour...	11/16/1982
4338616	Self-aligned Schottky metal semi-conductor field effect transistor with buried source and drain A semi-conductor structure and particularly a high speed VLSI Self-Aligned Schottky Metal Semi-Conductor Field Effect Transistor with buried source and drain, fabricated by the ion implantation of source and drain areas at a predetermined range of depths ...	07/06/1982
4310568	Method of fabricating improved Schottky barrier contacts An aluminum-transition metal Schottky barrier contact, and methods of fabrication thereof are disclosed. In one preferred embodiment, the junction is comprised of an aluminum-tantalum intermetallic layer abutting a silicon substrate. Alternate embodiments...	01/12/1982
4304042	Self-aligned MESFETs having reduced series resistance Disclosed herein is a structure and process for a self-aligned metal semiconductor field effect transistor having the characteristics of a high speed, high density, low power LSI circuit and specifically an improved high device gain MESFET device using co...	12/08/1981
4277883	Integrated circuit manufacturing method A method for forming a semiconductor structure is disclosed wherein a masking layer used to form the gate contact of a Metal Electrode Semiconductor Field Effect Transistor (MESFET) is formed by selectively depositing particles into separated regions of t...	07/14/1981
4272561	Hybrid process for SBD metallurgies A method for forming thin film patterns in the fabrication of integrated circuits utilizing a lift-off mask in an inverse vertical relationship with the desired metal film. The method involves the preliminary blanket deposition of the metal in-point, foll...	06/09/1981
4261095	Self aligned schottky guard ring A method of forming a self aligned guard ring surrounding a schottky barrier diode device without requiring an enlargement of the final schottky barrier device. The method involves creating an overhanging opening in a insulator layer overlying a semicondu...	04/14/1981
4253229	Self-aligned narrow gate MESFET process A method of making a narrow gate MESFET including the steps of placing a layered mask of nitride and polysilicon over a channel region for self-aligning in a substrate, oxidizing and then removing the polysilicon to reduce the remaining polysilicon width,...	03/03/1981
4254428	Self-aligned Schottky diode structure and method of fabrication A Schottky diode structure and self-aligned fabrication method wherein the cathode or ohmic contact is disposed in the center of the anode or Schottky contact and is isolated therefrom by an overlapping layer of insulation. This structure has a reduced ar...	03/03/1981
4222164	Method of fabrication of self-aligned metal-semiconductor field effect transistors A method for the production of metal-semiconductor field effect transistors (MESFET) is described. Practice of the method allows one to produce self-aligning MESFETs with Si sources and drains in close proximity having metal gates therebetween....	09/16/1980
4215156	Method for fabricating tantalum semiconductor contacts A silicon semiconductor device having contacts which include tantalum. The tantalum is useful in particular for fabricating Schottky barrier diodes having a low barrier height. The method includes: precleaning the silicon substrate prior to depositing the...	07/29/1980

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Class 257/E21.45 - With Schottky gate, e.g., MESFET (EPO)