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"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 6696706 | Structure and method for a junction field effect transistor with reduced gate capacitance An apparatus and method for a semiconductor device with reduced gate capacitance. Specifically, an n-channel or p-channel junction field effect transistor (JFET) is described comprising an appropriately doped substrate forming a drain region, an epitaxial... | 02/24/2004 |
| 6690040 | Vertical replacement-gate junction field-effect transistor A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of differ... | 02/10/2004 |
| 6580150 | Vertical junction field effect semiconductor diodes Semiconductor diodes are diode connected vertical cylindrical field effect devices having one diode terminal as the common connection between a gate and a source/drain of the vertical cylindrical field effect devices. Methods of forming the diode connecte... | 06/17/2003 |
| 6576929 | Silicon carbide semiconductor device and manufacturing method A channel layer 4 is formed on an n- -type epitaxial layer 2 and first gate areas 3, and field enhanced area(s) 5 and second gate areas 6 are formed on the first gate areas 3. Furthermore, n+ -type source areas 7 and a third gate are... | 06/10/2003 |
| 5861643 | Self-aligned JFET A JFET device is formed on a semiconductor body comprising an active region for the junction field effect device. A drain region layer is formed below the lower portion of the active region. The top surface of the body is doped to provide a source region ... | 01/19/1999 |
| 5702987 | Method of manufacture of self-aligned JFET A JFET device is formed on a semiconductor body comprising an active region for the junction field effect device. A drain region layer is formed below the lower portion of the active region. The top surface of the body is doped to provide a source region ... | 12/30/1997 |
| 5599724 | FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same An N-type source (or drain) region is formed in the surface area of a P-type silicon substrate. A first insulation film is formed on the silicon substrate and a gate electrode is formed on the first insulation film. A second insulation film is formed on t... | 02/04/1997 |
| 5340757 | Method of manufacturing a vertical field effect transistor In the method of manufacturing a vertical field effect transistor, the gate region situated on either side of the source region projecting from a main face of a semiconductive substrate consists in implanting ions on either side of the source region to fo... | 08/23/1994 |
| 5312782 | SOI type vertical channel field effect transistor and process of manufacturing the same A thin film field effect transistor manufactured using a cladding technique wherein parasitic capacities of the source and drain with respect to the ground are low and a substrate biasing effect is low. The vertical channel field effect transistor compris... | 05/17/1994 |
| 4505022 | Junction vertical field effect transistor and process for the production thereof This transistor comprises a first main surface of alternating source and gate strips. A gate metallization rests on the gate strips and a source metallization rests on a polycrystalline silicon rail formed above the source strips. Such a device can be man... | 03/19/1985 |
| 4351099 | Method of making FET utilizing shadow masking and diffusion from a doped oxide A novel self-align type method of making an FET with a very short gate length and a good high frequency characteristic, and a low noise characteristic, the method comprising the steps of: forming on a silicon epitaxial layer (13) of n-type conductivity a doped... | 09/28/1982 |
| 4288800 | Junction field effect transistor A vertical or horizontal type junction FET including a channel-gate structure formed by a double diffusion process in which two treatments for diffusing different impurities are executed through an identical opening provided in a diffusion mask. For fabri... | 09/08/1981 |
| 4181542 | Method of manufacturing junction field effect transistors A vertical or horizontal type junction FET including a channel-gate structure formed by a double diffusion process in which two treatments for diffusing different impurities are executed through an identical opening provided in a diffusion mask. For fabri... | 01/01/1980 |
| 4175317 | Method for manufacturing junction type field-effect transistors In a method for manufacturing a junction type field-effect transistor, there is formed a gate region having one portion over which a source electrode extends and the other portion which allows an essential gate function. These portions are formed by diffu... | 11/27/1979 |
| 3938241 | Vertical channel junction field-effect transistors and method of manufacture The disclosed junction field-effect transistor (FET) has a precisely controlled gate configuration which enables either high power operation or high frequency operation or both. The FET is manufactured by steps including the growing of a first epitaxial l... | 02/17/1976 |
