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| Number | Title | Issue Date |
| 7402494 | Method for fabricating high voltage semiconductor device A method for fabricating a high voltage semiconductor device, which comprises a semiconductor substrate; a gate insulation layer formed on the semiconductor substrate; and a gate electrode formed on the gate insulation layer, comprising: forming a mask pattern on th... | 07/22/2008 |
| 7279767 | Semiconductor structure with high-voltage sustaining capability and fabrication method of the same A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to th... | 10/09/2007 |
| 7268033 | Method and structure for providing tuned leakage current in CMOS integrated circuits A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjac... | 09/11/2007 |
| 7179714 | Method of fabricating MOS transistor having fully silicided gate There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate ... | 02/20/2007 |
| 7166506 | Poly open polish process A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with hi... | 01/23/2007 |
| 7119405 | Implantation method to improve ESD robustness of thick gate-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies An implantation method to improve ESD robustness of thick-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies. Based on standard process flow in DGO, a thick gate-oxide ESD device is improved. Instead of using the standard I/O device, the ESD device us... | 10/10/2006 |
| 7067880 | Transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate co... | 06/27/2006 |
| 6673663 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 01/06/2004 |
| 6674139 | Inverse T-gate structure using damascene processing A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the ce... | 01/06/2004 |
| 6664592 | Semiconductor device with groove type channel structure A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom ... | 12/16/2003 |
| 6653686 | Structure and method of controlling short-channel effect of very short channel MOSFET A semiconductor device comprising a gate having an approximately 0.05 μm channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the ... | 11/25/2003 |
| 6642581 | Semiconductor device comprising buried channel region A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gat... | 11/04/2003 |
| 6642130 | Method for fabricating highly integrated transistor A method for fabricating a transistor comprises steps of forming a conductive well region, an isolation oxide layer, a first pad oxide layer, a conductive LDD (low doped drain) region and a source/drain region on a silicon substrate. A pad nitride layer i... | 11/04/2003 |
| 6630710 | Elevated channel MOSFET The present invention provides a semiconductor device (e.g., MOSFET) having a channel above the surface of the wafer containing a well and a junction. The elevated channel may be selectively epitaxially grown and enables higher mobility, thereby enabling ... | 10/07/2003 |
| 6627488 | Method for fabricating a semiconductor device using a damascene process Disclosed herein is a method of fabricating a semiconductor device using a damascene process. The method comprises the steps of: forming a dummy gate electrode on a semiconductor substrate; forming a source/drain region in the substrate; polishing and pla... | 09/30/2003 |
| 6617633 | Vertical read-only memory and fabrication thereof A vertical read-only memory (ROM) is provided, which includes a gate on a substrate, a source/drain at the bottom of a trench in the substrate, a polysilicon bit-line in the trench, and a dielectric layer separating the polysilicon bit-line and the side-w... | 09/09/2003 |
| 6617226 | Semiconductor device and method for manufacturing the same In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating ... | 09/09/2003 |
| 6613621 | Methods of forming self-aligned contact pads using a damascene gate process Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the ... | 09/02/2003 |
| 6583017 | Self aligned channel implant, elevated S/D process by gate electrode damascene A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the la... | 06/24/2003 |
| 6566719 | Semiconductor integrated circuit The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as mask... | 05/20/2003 |
| 6566696 | Self-aligned VT implant Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a subst... | 05/20/2003 |
| 6562687 | MIS transistor and method for making same on a semiconductor substrate The invention relates to an MIS transistor comprising a channel region (118), source (114) and drain (116) regions arranged on either side of the channel, and a gate (150) set closely above the channel region. According to the invention, the channel has a... | 05/13/2003 |
| 6541829 | Semiconductor device and method of manufacturing the same A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor regio... | 04/01/2003 |
| 6503805 | Channel implant through gate polysilicon A field effect transistor having a doped region in the substrate immediately underneath the gate of the transistor and interposed between the source and drain of the transistor is provided. The doped region has a retrograde dopant profile such that the do... | 01/07/2003 |
| 6501131 | Transistors having independently adjustable parameters The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern ... | 12/31/2002 |
| 6492693 | Low voltage high performance semiconductor devices and methods A method for adjusting Vt while minimizing parasitic capacitance fiord low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded i... | 12/10/2002 |
| 6482691 | Seismic imaging using omni-azimuth seismic energy sources and directional sensing Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 11/19/2002 |
| 6479356 | Method of manufacturing a semiconductive device with an enhanced junction breakdown strength A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furn... | 11/12/2002 |
| 6475852 | Method of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 11/05/2002 |
| 6472260 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 10/29/2002 |
| 6465311 | Method of making a MOSFET structure having improved source/drain junction performance A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in ... | 10/15/2002 |
| 6458664 | Method for fabricating a field-effect transistor having an anti-punch-through implantation region A simple method for fabricating a field-effect transistor having an anti-punch-through implantation region is provided. After the anti-punch-through implantation region is formed, a semiconductor substrate is locally oxidized by using a mask layer in orde... | 10/01/2002 |
| 6413823 | Methods of forming field effect transistors Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 07/02/2002 |
| 6406957 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 06/18/2002 |
| 6400002 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 06/04/2002 |
| 6388294 | Integrated circuit using damascene gate structure An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffus... | 05/14/2002 |
| 6383876 | MOS device having non-uniform dopant concentration and method for fabricating the same A metal-oxide-semiconductor (MOS) device in which the nonuniform dopant concentration in the channel region is obtained by means of ion implantation through a polysilicon gate electrode of nonuniform cross section, which is itself obtained by oxidizing th... | 05/07/2002 |
| 6373102 | Process for fabricating a channel region of a transistor device with ion implantation and the transistor device formed therefrom The invention is related to a method for fabricating a channel region of a transistor device by ion implantation with a large angle and the transistor device formed therefrom. The transistor device is formed on a substrate. Furthermore, the ion implantati... | 04/16/2002 |
| 6344382 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 02/05/2002 |
| 6344397 | Semiconductor device having a gate electrode with enhanced electrical characteristics In one illustrative embodiment, the present invention is directed to forming a masking layer (104) above a semiconducting substrate (102), forming an opening (105) in the masking layer (104), forming sidewall spacers (109) that define an exposed surface o... | 02/05/2002 |
