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User-operated amusement apparatus for kicking the user's buttocks
An apparatus including a user-operated and controlled apparatus for self-infliction of repetitive blows to the user's buttocks by a plurality of elongated arms bearing flexible extensions that rotate under the user's control.
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| Number | Title | Issue Date |
| 7439574 | Silicon/oxide/nitride/silicon nonvolatile memory with vertical channels Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on t... | 10/21/2008 |
| 7436033 | Tri-gated molecular field effect transistor and method of fabricating the same A tri-gated molecular field effect transistor includes a gate electrode formed on a substrate and having grooves in a source region, a drain region and a channel region, and at least one molecule inserted between the source and drain electrodes in the channel region... | 10/14/2008 |
| 7422946 | Independently accessed double-gate and tri-gate transistors in same process flow A method for forming first and second devices from first and second silicon bodies is described. A sacrificial layer allows gate regions to be defined with underlying insulating members. After the sacrificial layer and bodies are surrounded in a dielectric layer, th... | 09/09/2008 |
| 7413955 | Transistor for memory device and method for manufacturing the same Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a gro... | 08/19/2008 |
| 7407845 | Field effect transistor and method for manufacturing the same In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other a... | 08/05/2008 |
| 7405127 | Method for producing a vertical field effect transistor A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electr... | 07/29/2008 |
| 7396761 | Semiconductor device and method of manufacturing the same In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewa... | 07/08/2008 |
| 7396726 | Methods of fabricating surrounded-channel transistors with directionally etched gate or insulator formation regions An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped ... | 07/08/2008 |
| 7384850 | Methods of forming complementary metal oxide semiconductor (CMOS) transistors having three-dimensional channel regions therein An integrated circuit device containing complementary metal oxide semiconductor transistors includes a semiconductor substrate and an NMOS transistor having a first fin-shaped active region that extends in the semiconductor substrate. The first fin-shaped active reg... | 06/10/2008 |
| 7358142 | Method for forming a FinFET by a damascene process A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and ... | 04/15/2008 |
| 7354832 | Tri-gate device with conformal PVD workfunction metal on its three-dimensional body and fabrication method thereof A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conform... | 04/08/2008 |
| 7332386 | Methods of fabricating fin field transistors A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides ... | 02/19/2008 |
| 7326656 | Method of forming a metal oxide dielectric A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first... | 02/05/2008 |
| 7326620 | Method of manufacturing a semiconductor device and semiconductor device obtainable with such a method A method of manufacturing a semiconductor device comprising a dual gate field effect transistor is disclosed, in which method a semiconductor body with a surface and of silicon is provided with a source region and a drain region of a first conductivity type and with... | 02/05/2008 |
| 7312504 | Transistor for memory device and method for manufacturing the same Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a gro... | 12/25/2007 |
| 7297581 | SRAM formation using shadow implantation A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant proce... | 11/20/2007 |
| 7297600 | Methods of forming fin field effect transistors using oxidation barrier layers A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An ... | 11/20/2007 |
| 7274053 | Fin device with capacitor integrated under gate electrode A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator c... | 09/25/2007 |
| 7271025 | Image sensor with SOI substrate An imager pixel utilizing a silicon-on-insulator substrate, a photodiode in said substrate below the buried oxide, and a dual contact to said photodiode and methods of forming said imager pixel. The photodiode has an increased fill factor due to its increased size r... | 09/18/2007 |
| 7244640 | Method for fabricating a body contact in a Finfet structure and a device including the same A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator subs... | 07/17/2007 |
| 7229889 | Methods for metal plating of gate conductors and semiconductors formed thereby A method of metal plating a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, and binding a seed layer to the one ... | 06/12/2007 |
| 7229867 | Process for producing a field-effect transistor and transistor thus obtained A substrate supporting a portion of a semiconductor material is used to produce a field-effect transistor. A portion of a temporary material lies between the portion of semiconductor material and the substrate. A gate is formed, which comprises an upper part in rigi... | 06/12/2007 |
| 7224033 | Structure and method for manufacturing strained FINFET A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is ... | 05/29/2007 |
| 7187046 | Method of forming an N channel and P channel finfet device on the same semiconductor substrate A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the ... | 03/06/2007 |
| 7176067 | Methods of fabricating fin field effect transistors A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active reg... | 02/13/2007 |
| 7176092 | Gate electrode for a semiconductor fin device A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and... | 02/13/2007 |
| 7122871 | Integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit subs... | 10/17/2006 |
| 7074662 | Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage A method of forming a fin field effect transistor on a semiconductor substrate includes forming a vertical fin protruding from the substrate. A buffer oxide liner is formed on a top surface and on sidewalls of the fin. A trench is then formed on the substrate, where... | 07/11/2006 |
| 6693324 | Semiconductor device having a thin film transistor and manufacturing method thereof A semiconductor layer has one end placed on top of a first conductive layer and in contact with the first conductive layer, and the other end placed on top of a second conductive layer and in contact with the second conductive layer. At the central portio... | 02/17/2004 |
| 6689650 | Fin field effect transistor with self-aligned gate The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion j... | 02/10/2004 |
| 6664582 | Fin memory cell and method of fabrication The present invention provides a memory cell and method for forming the same that results in improved cell density without overly increasing fabrication cost and complexity. The preferred embodiment of the present invention provides a fin design to form t... | 12/16/2003 |
| 6660596 | Double planar gated SOI MOSFET structure A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographic... | 12/09/2003 |
| 6657259 | Multiple-plane FinFET CMOS The present invention provides FinFETs on the same substrate utilizing various crystal planes for FET current channels in order to optimize mobility and/or to reduce mobility. An embodiment of the present invention provides a substrate having a surface or... | 12/02/2003 |
| 6653687 | Insulated gate semiconductor device Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel e... | 11/25/2003 |
| 6649455 | SOI type MOS element and manufacturing method thereof To present a SOI type MOS element excellent in yield, performance and characteristic, easy in manufacture, and low in cost, and a method of manufacturing the same. A SOI type MOS transistor structure comprising polysilicon electrodes 128 for gate, source ... | 11/18/2003 |
| 6649935 | Self-aligned, planarized thin-film transistors, devices employing the same A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect... | 11/18/2003 |
| 6645797 | Method for forming fins in a FinFET device using sacrificial carbon layer A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mas... | 11/11/2003 |
| 6642090 | Fin FET devices from bulk semiconductor and method for forming The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET ... | 11/04/2003 |
| 6635923 | Damascene double-gate MOSFET with vertical channel regions A technique for forming a sub-0.05 μm channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive techniqu... | 10/21/2003 |
| 6630388 | Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insu... | 10/07/2003 |
