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| Number | Title | Issue Date |
| 7432180 | Method of fabricating a nickel silicide layer by conducting a thermal annealing process in a silane gas A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nic... | 10/07/2008 |
| 7429525 | Fabrication process of a semiconductor device A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing... | 09/30/2008 |
| 7378344 | Method of manufacturing a semiconductor device including a silicide layer having an NiSi phase provided on source and drain regions A method for manufacturing a MOSFET equipped with a silicide layer over shallow source and drain junctions without leakage generation is provided. By restricting the temperature of manufacturing steps after the silicide formation below a critical temperature Tc, whi... | 05/27/2008 |
| 7375025 | Method for forming a metal silicide layer in a semiconductor device On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are remove... | 05/20/2008 |
| 7348248 | CMOS transistor with high drive current and low sheet resistance A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate dielectric over a substrate, a gate electrode over the gate dielectric, a slim gate spacer along a side of the gate electrode, and a source/drain re... | 03/25/2008 |
| 7329604 | Semiconductor device and method for fabricating the same The method for fabricating a semiconductor device comprises the step of forming a Co film 72 on a gate electrode 30 having a gate length Lg of below 50 nm including 50 nm; the first thermal processing step of making thermal processing to rea... | 02/12/2008 |
| 7319063 | Fin field effect transistor and method for manufacturing fin field effect transistor The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed... | 01/15/2008 |
| 7297618 | Fully silicided gate electrodes and method of making the same The present invention relates to a method of selectively fabricating metal gate electrodes in one or more device regions by fully siliciding (FUSI) the gate electrode. The selective formation of FUSI enables metal gate electrodes to be fabricated on devices that are... | 11/20/2007 |
| 7271455 | Formation of fully silicided metal gate using dual self-aligned silicide process An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of for... | 09/18/2007 |
| 7244996 | Structure of a field effect transistor having metallic silicide and manufacturing method thereof A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces... | 07/17/2007 |
| 7129548 | MOSFET structure with multiple self-aligned silicide contacts A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field eff... | 10/31/2006 |
| 6693013 | Semiconductor transistor using L-shaped spacer and method of fabricating the same The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside th... | 02/17/2004 |
| 6673665 | Semiconductor device having increased metal silicide portions and method of forming the semiconductor The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed such that an upper portion of the line sidewall is exposed s... | 01/06/2004 |
| 6657244 | Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation A method of fabricating a semiconductor structure where a low gate resistance is obtained, while simultaneously reducing silicon consumption in the source/drain diffusion regions. The method provides a semiconductor structure having a thin silicide region... | 12/02/2003 |
| 6649976 | Semiconductor device having metal silicide film and manufacturing method thereof A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted ... | 11/18/2003 |
| 6642119 | Silicide MOSFET architecture and method of manufacture The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in con... | 11/04/2003 |
| 6635539 | Method for fabricating a MOS transistor using a self-aligned silicide technique A method for fabricating a MOS transistor using a self-aligned silicide technique is provided. The method includes forming a gate electrode and a silicidation resistant layer pattern that are sequentially stacked on a predetermined region of a semiconduct... | 10/21/2003 |
| 6620718 | Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device The present invention is directed to a method of forming metal silicide regions on a gate electrode (23) and on the source/drain regions (25) of a semiconductor device (100). In one illustrative embodiment, the method comprises forming a gate stack (17) a... | 09/16/2003 |
| 6548877 | Metal oxide semiconductor field effect transistor for reducing resistance between source and drain A MOS field effect transistor for reducing the resistance between a source and a drain includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate includes deep source/drain regions formed in upper portions of th... | 04/15/2003 |
| 6534405 | Method of forming a MOSFET device featuring a dual salicide process A method for fabricating a MOSFET device using a dual salicide formation procedure has been developed. The process features a first salicide formation procedure used to create a thick metal silicide component for a composite gate structure, with the compo... | 03/18/2003 |
| 6528402 | Dual salicidation process A dual salicidation process has the steps of: covering a sacrificial layer on the top of a polysilicon gate conductor; performing a thermal oxidization process to form a poly-oxide spacer on the sidewall of the polysilicon gate conductor; forming source/d... | 03/04/2003 |
| 6524939 | Dual salicidation process A dual salicidation process is used on a semiconductor substrate which has a gate dielectric, a polysilicon gate conductor patterned upon a predetermined area of the gate dielectric, a sacrificial layer patterned upon the polysilicon gate conductor, and L... | 02/25/2003 |
| 6482739 | Method for decreasing the resistivity of the gate and the leaky junction of the source/drain This invention relates to a method for decreasing the resistivity of the gate and leaky junction of the source/drain, more particularly, to the method for forming a metal silicide layer at the gate region and the source/drain region by using two times in ... | 11/19/2002 |
| 6458678 | Transistor formed using a dual metal process for gate and source/drain region A method for forming a semiconductor device includes providing a substrate and forming a gate stack on the substrate. The gate stack includes a gate electrode having a thickness. Source/drain regions are formed in the substrate proximate the gate stack, a... | 10/01/2002 |
| 6413807 | Semiconductor device having silicide films on a gate electrode and a diffusion layer and manufacturing method thereof Silicide films having a high heat-resistance are formed on a gate electrode, simultaneously with silicide films having good junction leakage characteristics on diffusion layers. A transistor includes a polycrystalline silicon gate electrode, a gate insula... | 07/02/2002 |
| 6387786 | Method of salicide formation by siliciding a gate area prior to siliciding a source and drain area The present invention relates to a method of forming a self-aligned silicide (salicide) by siliciding a gate area prior to siliciding a source and drain area and/or spacer formation. The method improves transistor speed by lowering the leakage current in ... | 05/14/2002 |
| 6297135 | Method for forming silicide regions on an integrated device The invented method can be used to form silicide contacts to an integrated MISFET device. Field isolation layers are formed to electrically isolate a portion of the silicon substrate, and gate, source and drain regions are formed therein. A polysilicon ru... | 10/02/2001 |
| 6291354 | Method of fabricating a semiconductive device A method of fabricating a semiconductor device is described in which an insulation layer is formed over the gate electrode and the substrate. This insulation layer is anisotropically etched away except for a portion surrounding the sidewall of the gate el... | 09/18/2001 |
| 6281086 | Semiconductor device having a low resistance gate conductor and method of fabrication the same A semiconductor device and a method of fabricating the same is provided, wherein the semiconductor device exhibits a lower gate delay time when compared to that of a conventional semiconductor device. The reduction of gate delay time is achieved by provid... | 08/28/2001 |
| 6274450 | Method for implementing metal oxide semiconductor field effect transistor A method for manufacturing metal oxide semiconductor field effect transistor is disclosed. The metal oxide semiconductor field effect transistor is formed by a specific fabricating process that disadvantages of thermal damage are effectively prevented. Ac... | 08/14/2001 |
| 6271133 | Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication A new method is established to form different silicide layers over the top of the gate electrode and the surface of the source/drain regions. A thin layer of TiSi2 is formed over the source/drain regions by depositing a layer of titanium and an... | 08/07/2001 |
| 6268257 | Method of forming a transistor having a low-resistance gate electrode A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance port... | 07/31/2001 |
| 6242776 | Device improvement by lowering LDD resistance with new silicide process A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and removing a first portion of the ... | 06/05/2001 |
| 6235566 | Two-step silicidation process for fabricating a semiconductor device A two-step silicidation process for fabricating a semiconductor device is disclosed. The method includes the following steps. Firstly, two trench isolation regions are formed in a semiconductor substrate. A gate oxide layer and a polysilicon layer and a b... | 05/22/2001 |
| 6228724 | Method of making high performance MOSFET with enhanced gate oxide integration and device formed thereby Transistors formed according to the present invention include an oxide layer/nitride layer gate insulator and a silicide gate conductor. An oxide layer is formed to a thickness of between 15 and 25 Angstroms across a substrate and partially removed so tha... | 05/08/2001 |
| 6228722 | Method for fabricating self-aligned metal silcide A method of fabricating a self-aligned metal silicide. Two neighboring gates are formed on a substrate, and each of the gates comprises a cap layer thereon. Source/drain regions are formed in the substrate. The source/drain regions comprise a common sourc... | 05/08/2001 |
| 6218716 | Enhanced structure for salicide MOSFET A method for increasing salicide thickness and effective polysilicon width at a narrow polysilicon line while reducing resistance and reducing source/drain bridging risk in the fabrication of a silicided polysilicon gate is described. A polysilicon layer ... | 04/17/2001 |
| 6207543 | Metallization technique for gate electrodes and local interconnects A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating with an oxide layer, planarizing the layer, then forming a t... | 03/27/2001 |
| 6187675 | Method for fabrication of a low resistivity MOSFET gate with thick metal silicide on polysilicon The present invention is a method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the gate having low resistivity. The MOSFET has a drain region, a source region, and a channel region fabricated within a semicon... | 02/13/2001 |
| 6184115 | Method of fabricating self-aligned silicide The present invention is directed towards a method of fabricating a self-aligned silicide on gate electrode and source/drain region of a semiconductor device. A semiconductor substrate having gate oxide layer and polysilicon layer is provided. Next, a fir... | 02/06/2001 |
