Class 257/E21.437 - With lightly doped drain selectively formed at side of gate (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.409. This
No. of patents: 137
Last issue date: 04/24/2007

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Number	Title	Issue Date
7208384	Transistors and manufacturing methods thereof Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region...	04/24/2007
7163868	Method for forming a lightly doped drain in a thin film transistor In accordance with the present invention, a gate electrode structure with inclined planes is used as a mask when performing an ion implantation process. The inclined planes are used to define the lightly doped drain (LDD) region in the active area. Therefore, the wi...	01/16/2007
7135373	Reduction of channel hot carrier effects in transistor devices A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shal...	11/14/2006
7095086	Semiconductor devices and methods of manufacturing the same Semiconductor devices and methods of manufacturing the same are provided. A disclosed semiconductor device includes: a semiconductor substrate; a gate insulating layer on the active region of the semiconductor substrate; a gate on the gate insulating layer; LDD regi...	08/22/2006
6703659	Low voltage programmable and erasable flash EEPROM A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlyi...	03/09/2004
6693335	Semiconductor raised source-drain structure A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the d...	02/17/2004
6686636	Semiconductor raised source-drain structure A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication wi...	02/03/2004
6683355	Semiconductor raised source-drain structure A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication wi...	01/27/2004
6677208	Transistor with bottomwall/sidewall junction capacitance reduction region and method A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a gate insulator and sidewalls and forming source region and a drain region in the substrate using...	01/13/2004
6674139	Inverse T-gate structure using damascene processing A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the ce...	01/06/2004
6667216	Semiconductor device and method of fabricating the same A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substra...	12/23/2003
6667512	Asymmetric retrograde halo metal-oxide-semiconductor field-effect transistor (MOSFET) An asymmetric retrograde HALO Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) includes a semiconductor substrate. A gate is formed over the substrate, the gate defining a channel thereunder in the substrate having a source side and a drain side...	12/23/2003
6642122	Dual laser anneal for graded halo profile Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphiz...	11/04/2003
6624035	Method of forming a hard mask for halo implants The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a surface of a semiconducting substrate, and forming a hard mask layer ab...	09/23/2003
6617219	Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors A method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extensi...	09/09/2003
6617229	Method for manufacturing transistor of double spacer structure A method for manufacturing a transistor of a double spacer structure is disclosed, in which a local LDD region is formed by forming a transistor including a gate electrode, and an oxide film spacer and a nitride film spacer formed sequentially, dry etchin...	09/09/2003
6599840	Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi...	07/29/2003
6599804	Fabrication of field-effect transistor for alleviating short-channel effects Short-channel threshold voltage roll-off and punchthrough in an IGFET (40 or 42) having a channel zone (64 or 84) situated in body material (50) are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a loc...	07/29/2003
6596648	Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi...	07/22/2003
6597045	Semiconductor raised source-drain structure A semiconductor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication w...	07/22/2003
6596642	Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi...	07/22/2003
6596606	Semiconductor raised source-drain structure A method of forming a semiconductor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping laye...	07/22/2003
6583017	Self aligned channel implant, elevated S/D process by gate electrode damascene A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the la...	06/24/2003
6566734	Semiconductor device In making a field effect transistor, a dummy gate electrode is formed before a gate electrode is formed. Extension regions, a side wall silicon nitride film, source/drain regions, a silicon oxide film, and other elements are formed with respect to the dum...	05/20/2003
6562683	Bit-line oxidation by removing ONO oxide prior to bit-line implant A method for fabricating a semiconductor structure includes forming a masking pattern on an ONO layer, wherein the ONO layer is on a semiconductor substrate, forming pocket regions in the substrate with the masking pattern as a doping mask, etching the ON...	05/13/2003
6548862	Structure of semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low para...	04/15/2003
6548842	Field-effect transistor for alleviating short-channel effects An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local su...	04/15/2003
6544851	Method of manufacturing a semiconductor device having a pocket implant in channel region In a method of manufacturing a semiconductor device comprising a semiconductor body (1) of a first conductivity type which is provided at a surface (2) with a transistor having a gate (28) insulated from a channel (13) provided at the surface (2) of the s...	04/08/2003
6541357	Semiconductor device and method of manufacturing the same There is disclosed a semiconductor device having: a semiconductor substrate; a first gate electrode constructed of a multi-layered stack member provided in a memory region, formed with memory cells, of a surface area of the semiconductor substrate so that...	04/01/2003
6531380	Method of fabricating T-shaped recessed polysilicon gate transistors A method of fabricating a semiconductor transistor device comprising the following steps. A semiconductor structure is provided having an upper silicon layer, a pad dielectric layer over the upper silicon layer, and a well implant within a well region in ...	03/11/2003
6524919	Method for manufacturing a metal oxide semiconductor with a sharp corner spacer A method for manufacturing a metal oxide semiconductor device is provided comprising the steps of: performing an ion implantation to form a source/drain region in the substrate having a gate formed on it and a spacer formed on the sidewalls of the gate; f...	02/25/2003
6518122	Low voltage programmable and erasable flash EEPROM A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlyi...	02/11/2003
6501131	Transistors having independently adjustable parameters The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern ...	12/31/2002
6492670	Locally confined deep pocket process for ULSI MOSFETS A method of fabricating an integrated circuit with locally confined deep pocket regions utilizes a dummy or sacrificial gate spacer. Dopants are provided through the openings associated with sacrificial spacers to form the pocket regions. The dopants are ...	12/10/2002
6492696	Semiconductor device and process of manufacturing the same A semiconductor device comprises: gate electrode formed on a semiconductor substrate through the intervention of a gate insulating film; and a source/drain region provided with a silicide film on its surface and formed in the semiconductor substrate, wher...	12/10/2002
6489223	Angled implant process Different symmetrical and asymmetrical devices are formed on the same chip using non-critical block masks and angled implants. A barrier is selectively formed adjacent one side of a structure and this barrier blocks dopant implanted at an angle toward the...	12/03/2002
6489206	Method for forming self-aligned local-halo metal-oxide-semiconductor device A method for forming a self-aligned local-halo metal-oxide-semiconductor device is provided. The present method is characterized in that a pair of first sidewall spacers is firstly formed on opposite sides of a gate electrode over a semiconductor substrat...	12/03/2002
6482724	Integrated circuit asymmetric transistors A method to form asymmetric MOS transistors using a replacement gate design. The method involves forming implanted regions (140) and (145) in the channel region after removal of the replacement gate structure (110) to produce high threshold voltage region...	11/19/2002
6461967	Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi...	10/08/2002
6458665	Halo ion implantation method for fabricating a semiconductor device The present invention relates to a halo ion implantation method for a semiconductor device, and in a semiconductor device formed of a cell array region with a relatively high concentration of pattern and a peripheral circuit region with a relatively low c...	10/01/2002

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Class 257/E21.437 - With lightly doped drain selectively formed at side of gate (EPO)