Class 257/E21.435 - Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.409. This
No. of patents: 1081
Last issue date: 07/08/2008

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
7397075	Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted region...	07/08/2008
7387924	Polycrystalline SiGe junctions for advanced devices A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers a...	06/17/2008
7384835	Metal oxide field effect transistor with a sharp halo and a method of forming the transistor Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. T...	06/10/2008
7371649	Method of forming carbon-containing silicon nitride layer A method for forming a carbon-containing silicon nitride layer with superior uniformity by low pressure chemical vapor deposition (LPCVD) using disilane, ammonia and at least one carbon-source precursor as reactant gases is provided. ...	05/13/2008
7368339	Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted region...	05/06/2008
7365009	Structure of metal interconnect and fabrication method thereof A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric condu...	04/29/2008
7332425	Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 located in a dielectric layer 135 of a substrate 1...	02/19/2008
7323377	Increasing self-aligned contact areas in integrated circuits using a disposable spacer In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material ...	01/29/2008
7306980	Method for fabricating thin film transistor A number of minuscule LDD thin film transistors with high precision are arranged on a substrate for use in a liquid crystal display apparatus or other similar devices. The gate electrode is used as a mask at the time of injecting impurities into the semiconductor la...	12/11/2007
7253478	Semiconductor device The semiconductor device comprises: a semiconductor substrate (N+ substrate 110) containing a first conductivity type impurity implanted therein; a second conductivity type impurity-implanted layer (P+ implanted layer 114) at rela...	08/07/2007
7235153	System for removal of a spacer The present disclosure provides a system for removing a spacer, such as associated with a processing operation using a lightly doped drain (LDD) region. In one example, the system includes means for creating a spacer, means for implanting a first relatively heavily ...	06/26/2007
7232730	Method of forming a locally strained transistor A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the...	06/19/2007
7221021	Method of forming high voltage devices with retrograde well A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the...	05/22/2007
7217604	Structure and method for thin box SOI device A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the devic...	05/15/2007
7214575	Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted region...	05/08/2007
7214577	Method of fabricating semiconductor integrated circuit device A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target ha...	05/08/2007
7211491	Method of fabricating gate electrode of semiconductor device A method of fabricating a gate electrode of a semiconductor device is disclosed. A disclosed method comprises growing a silicon epitaxial layer on a silicon substrate; making at least one trench through the epitaxial layer and filling the trench with a first oxide l...	05/01/2007
7211492	Self aligned metal gates on high-k dielectrics A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall ...	05/01/2007
7202134	Method of forming transistors with ultra-short gate feature A gate electrode is formed over but insulated from a semiconductor body region for each of first and second transistors. A DDD implant is carried out to from DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, off-set...	04/10/2007
7189660	Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic laye...	03/13/2007
7166893	Semiconductor integrated circuit device A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater tha...	01/23/2007
7157779	Semiconductor device with triple surface impurity layers An operational withstand voltage of a high voltage MOS transistor is enhanced and a variation in a saturation current Idsat is suppressed. A gate insulation film is formed on a P-type semiconductor substrate. A gate electrode is formed on the gate insulation film. A...	01/02/2007
7138689	Semiconductor device and manufacturing method thereof A semiconductor substrate that has a MOS transistor with a high breakdown voltage having double sidewall insulation films and can inhibit negative effects on the electric characteristics and method thereof. The semiconductor device is formed as a transistor with a c...	11/21/2006
7135373	Reduction of channel hot carrier effects in transistor devices A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shal...	11/14/2006
7122435	Methods, systems and structures for forming improved transistors A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Amorphous silicon regions are then fo...	10/17/2006
7119408	Semiconductor device and method for fabricating the same A semiconductor device of the present invention includes, as a peripheral MIS transistor 25b, a gate insulating film 13b and a gate electrode 14b provided above an active region 10b, first and second sidewalls ...	10/10/2006
7067880	Transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate co...	06/27/2006
7064021	Method for fomring a self-aligned LTPS TFT A method for forming a self-aligned low temperature polysilicon thin film transistor (LTPS TFT). First, active layers of a N type LTPS TFT (NLTPS TFT) and a P type LTPS TFT (PLTPS TFT) are formed on a substrate, and a gate insulating (GI) layer is formed on the subs...	06/20/2006
6881633	Method of manufacturing a semiconductor device with an L-shaped/reversed L-shaped gate side-wall insulating film Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-...	04/19/2005
6682994	Methods for transistor gate formation using gate sidewall implantation Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is em...	01/27/2004
6667525	Semiconductor device having hetero grain stack gate A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate ins...	12/23/2003
6614081	High-performance MOS transistor of LDD structure having a gate insulating film with a nitride central portion and oxide end portions A Metal Oxide Semiconductor (MOS) transistor includes a gate insulating film disposed on a surface of a silicon substrate. The gate insulating film has a central portion formed on the silicon substrate and comprising a nitride insulating film, and an end ...	09/02/2003
6593623	Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (5...	07/15/2003
6586306	Method for fabricating semiconductor device A method for fabricating a semiconductor device is disclosed. In a high speed device structure consisting of a salicide, in order to fabricate a device having at least two gate oxide structures in the identical chip, an LDD region of a core device region ...	07/01/2003
6582995	Method for fabricating a shallow ion implanted microelectronic structure Within a method for fabricating a microelectronic fabrication comprising a topographic microelectronic structure formed over a substrate, there is implanted, while employing a first ion implant method and while masking a portion of the substrate adjacent ...	06/24/2003
6579770	Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled po...	06/17/2003
6576939	Semiconductor processing methods, methods of forming electronic components, and transistors In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers respectively have an exposed outer edge spaced inside of the subst...	06/10/2003
6573166	Method of fabricating a LDD with different resistance value A method of fabricating lightly doped drains (LDD) of different resistance values starts by providing a semiconductor wafer, the semiconductor wafer having a first active area and a second active area positioned on the substrate. Secondly, a first gate an...	06/03/2003
6573133	Method of forming spacers in CMOS devices A sidewall spacer is formed in a CMOS device by depositing a layer of silicon nitride on a wafer and anisotropically etching away the silicon nitride layer with a chorine-based plasma etchant....	06/03/2003
6566719	Semiconductor integrated circuit The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as mask...	05/20/2003

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Quotables

PatentStorm News

Class 257/E21.435 - Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)