Class 257/E21.434 - With initial gate mask or masking layer complementary to prospective gate location, e.g., with dummy source and drain contacts (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.433. This
No. of patents: 217
Last issue date: 04/01/2008

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Number	Title	Issue Date
7351659	Methods of forming a transistor with an integrated metal silicide gate electrode Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal si...	04/01/2008
7285449	Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source /drain and semiconductor device manufactured by the method A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electro...	10/23/2007
7232731	Method for fabricating transistor of semiconductor device A method for fabricating a transistor of semiconductor is disclosed. A disclosed method comprises: forming an STI structure and a well region in a silicon substrate; forming a first dummy gate electrode including spacers and a first gate oxide layer on the well regi...	06/19/2007
7135363	Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla...	11/14/2006
6680504	Method for constructing a metal oxide semiconductor field effect transistor A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (...	01/20/2004
6674139	Inverse T-gate structure using damascene processing A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the ce...	01/06/2004
6673663	Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ...	01/06/2004
6664195	Method for forming damascene metal gate The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a poly...	12/16/2003
6656810	Semiconductor device capable of reducing dispersion in electrical characteristics and operating at high speed and method for fabricating the same There is provided a semiconductor device capable of reducing dispersion in electrical characteristics, preventing occurrence of bridge shortcircuit in a silicide process and operating at high operating speed and method for fabricating the same. In a SOI s...	12/02/2003
6656808	Transistor having variable width gate electrode and method of manufacturing the same A transistor includes a substrate and a gate electrode formed on the substrate and having a wider upper portion than lower portion. A spacer is formed on the side wall of the gate electrode from the upper portion to the lower portion of the gate electrode...	12/02/2003
6653686	Structure and method of controlling short-channel effect of very short channel MOSFET A semiconductor device comprising a gate having an approximately 0.05 μm channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the ...	11/25/2003
6642592	Semiconductor device and method for fabricating same A semiconductor device and method for fabricating the same which improves reliability of the semiconductor device is disclosed. The semiconductor device includes: a first insulating film and a gate electrode sequentially formed on a part of a semiconducto...	11/04/2003
6638843	Method for forming a silicide gate stack for use in a self-aligned contact etch A method for forming a gate stack having a silicide layer that can subsequently undergo a SAC etch is disclosed. The present method provides a layer of insulating material on top of the silicide layer. The insulating material is sufficient to protect the ...	10/28/2003
6639288	Semiconductor device with a particular conductor arrangement A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high a...	10/28/2003
6627526	Method for fabricating a conductive structure for a semiconductor device A process for making semiconductor structures, and the resulting highly conductive semiconductor structures, includes using damascene process to form a structure with a thin adhesive layer and overlaying conductive layer. The highly conductive semiconduct...	09/30/2003
6627503	Method of forming a multilayer dielectric stack A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallizatio...	09/30/2003
6617216	Quasi-damascene gate, self-aligned source/drain methods for fabricating devices Methods for use in fabricating integrated circuit structures. One embodiment of the present invention is a quasi-damascene gate, self-aligned source/drain method for forming a device on a substrate that includes steps of: (a) forming a gate dielectric lay...	09/09/2003
6613658	MIS field effect transistor and method of manufacturing the same There is disclosed a MIS field effect transistor, comprising a silicon substrate, an insulating film formed over the silicon substrate and containing silicon and at least one of nitrogen and oxygen, a metal oxynitride film formed on the insulating film an...	09/02/2003
6566696	Self-aligned VT implant Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a subst...	05/20/2003
6566216	Method of manufacturing a trench transistor To provide a semiconductor device and a process for manufacturing the same which is capable of suppressing short channel effect and preventing a current from leaking between a contact and a silicon substrate. The semiconductor device of the present invent...	05/20/2003
6555425	Method for manufacturing transistor A method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the p...	04/29/2003
6541829	Semiconductor device and method of manufacturing the same A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor regio...	04/01/2003
6531368	Method of fabricating a semiconductor device having a metal oxide high-k gate insulator by localized laser irradiation and a device thereby formed A method of fabricating a semiconductor device, having a locally-formed metal oxide high-k gate insulator, involving: nitriding a substrate to form a thin silicon nitride layer; depositing a thin metal film on the thin silicon nitride layer; forming a loc...	03/11/2003
6531410	Intrinsic dual gate oxide MOSFET using a damascene gate process Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as...	03/11/2003
6531781	Fabrication of transistor having elevated source-drain and metal silicide A method of forming a transistor, the method comprises following steps: provides a substrate; covers part of the substrate by a doped amorphous silicon layer and covers part of the substrate by a first dielectric layer; forms a metal silicide layer on the...	03/11/2003
6524916	Controlled gate length and gate profile semiconductor device and manufacturing method therefor An ultra-large scale integrated circuit semiconductor device is provided which has inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrie...	02/25/2003
6518625	Semiconductor device An n-type impurity layer is formed on a boundary portion between a source/drain and a field oxide film in a portion deeper than the source/drain. Even if a metal silicide layer such as a Co silicide layer extends into a portion under the field oxide film ...	02/11/2003
6506670	Self aligned gate A method for making a gate in an integrated circuit. A gate layer is formed on a substrate, and a blocking layer is formed on the gate layer. The blocking layer is masked with a photoresist layer, and the photoresist layer is developed to define an expose...	01/14/2003
6506639	Method of forming low resistance reduced channel length transistors Methods of manufacturing semiconductor devices having low resistance reduced channel length transistors. Spacers are formed on each side of trenches that define the location of transistor channels. The spacers are formed with a dimension between the space...	01/14/2003
6504210	Fully encapsulated damascene gates for Gigabit DRAMs A fully polysilicon encapsulated metal-containing damascene gate structure is provided that is useful in Gigabit DRAM (dynamic random access memory) device. The fully encapsulated metal-containing damascene gate comprises a semiconductor substrate having ...	01/07/2003
6503807	MOS transistor with two empty side slots on its gate and its method of formation A MOS transistor includes a substrate, an insulation layer, a gate and a dielectric layer. The substrate includes a drain and a source separately positioned on the surface of the substrate. The insulation layer is positioned on the surface of the substrat...	01/07/2003
6501131	Transistors having independently adjustable parameters The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern ...	12/31/2002
6482691	Seismic imaging using omni-azimuth seismic energy sources and directional sensing Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ...	11/19/2002
6483148	Self-aligned elevated transistor A method of forming a self-aligned elevated transistor using selective epitaxial growth is described. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having ...	11/19/2002
6479356	Method of manufacturing a semiconductive device with an enhanced junction breakdown strength A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furn...	11/12/2002
6475852	Method of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ...	11/05/2002
6472284	Method for fabricating a MOSFET having a thick and thin pad oxide at the gate sides A MOS transistor and a method for fabricating the MOS transistor which includes the forming a gate electrode containing an HLD film; etching the HLD film; etching a pad oxide film formed at a lower portion of the HLD film at a predetermined thickness; rem...	10/29/2002
6472260	Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ...	10/29/2002
6461529	Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas ...	10/08/2002
6461904	Structure and method for making a notched transistor with spacers A method of forming a semiconductor structure includes filling a trench in a first dielectric layer with a gate material. The first dielectric layer is on a semiconductor substrate, and spacers are in the trench. A semiconductor device formed from this st...	10/08/2002

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Class 257/E21.434 - With initial gate mask or masking layer complementary to prospective gate location, e.g., with dummy source and drain contacts (EPO)