Class 257/E21.433 - Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.424. This
No. of patents: 544
Last issue date: 10/07/2008

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Number	Title	Issue Date
7432144	Method for forming a transistor for reducing a channel length A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorp...	10/07/2008
7427549	Method of separating a structure in a semiconductor device Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions of different heights. In one example, the structure is removed by forming a spacer over the lower portion adjacent to the sidewall of the higher por...	09/23/2008
7393766	Process for integration of a high dielectric constant gate insulator layer in a CMOS device A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polys...	07/01/2008
7232720	Method for fabricating a semiconductor device having an insulation film with reduced water content A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the ...	06/19/2007
7217622	Semiconductor device and method of manufacturing the semiconductor device In a method of manufacturing a semiconductor device to improve structural stability of a semiconductor device in a silicidation process, a substrate is provided to have an active region defined by an isolation layer. An etching mask is formed on the active region an...	05/15/2007
6690070	Insulated gate semiconductor device and its manufacturing method A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. ...	02/10/2004
6667513	Semiconductor device with compensated threshold voltage and method for making same A semiconductor device may include a channel region formed between a source and a drain region. One or more first pockets may be formed in the channel region adjacent to junctions. The first pockets may be doped with a dopant of the first conductivity typ...	12/23/2003
6656799	Method for producing FET with source/drain region occupies a reduced area A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide...	12/02/2003
6653687	Insulated gate semiconductor device Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel e...	11/25/2003
6642560	MOSFET with a thin gate insulating film A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4...	11/04/2003
6642591	Field-effect transistor A field-effect transistor includes a silicon substrate on which is formed a channel region, a source region and a drain region. A gate insulation layer of a transition metal oxide having a perovskite structure is formed over at least the channel region, a...	11/04/2003
6635938	Semiconductor device and manufacturing method thereof A polysilicon nitride film is formed to cover a polysilicon gate. By heat treatment of the silicon nitride film in an oxygen atmosphere, a silicon oxinitride film is formed. By anisotropically etching the silicon oxinitride film and the silicon nitride fi...	10/21/2003
6632728	Increasing the electrical activation of ion-implanted dopants We have found that under certain prescribed conditions a co-implantation process can be effective in increasing the electrical activation of implanted dopant ions. In accordance with one aspect of our invention, a method of making a semiconductor device i...	10/14/2003
6599840	Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi...	07/29/2003
6596642	Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi...	07/22/2003
6596648	Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi...	07/22/2003
6593633	Method and device for improved salicide resistance on polysilicon gates The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Anothe...	07/15/2003
6593450	2,7-aryl-9-substituted fluorenes and 9-substituted fluorene oligomers and polymers The invention relates to 2,7-substituted-9-substituted fluorenes and 9-substituted fluorene oligomers and polymers. The fluorenes, oligomers and polymers are substituted at the 9-position with two hydrocarbyl moieties which may optionally contain one or m...	07/15/2003
6563179	MOS transistor and method for producing the transistor Terminal regions of source/drain zones of an MOS transistor are configured over the substrate in the form of conductive structures, are separated from the substrate by separating layers, and exhibit a larger horizontal cross-section than doped regions for...	05/13/2003
6541327	Method to form self-aligned source/drain CMOS device on insulated staircase oxide A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard m...	04/01/2003
6534827	MOS transistor Ion implantation is conducted using contact holes of a MOS transistor as.a mask to form high concentration diffusion regions, whereby a MOS transistor having a medium withstand voltage structure is provided, in which a high drain withstand voltage, a smal...	03/18/2003
6521527	Semiconductor device and method of fabricating the same Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+ -type gate electrode which are formed on...	02/18/2003
6515340	Semiconductor device A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide...	02/04/2003
6507058	Low threshold compact MOS device with channel region formed by outdiffusion of two regions and method of making same A compact metal oxide semiconductor (MOS) device has its channel region formed by the lateral extension of two high voltage (HV) regions. The two HV regions are implanted into a well region and, as a result of an annealing process, undergo outdiffusion an...	01/14/2003
6503805	Channel implant through gate polysilicon A field effect transistor having a doped region in the substrate immediately underneath the gate of the transistor and interposed between the source and drain of the transistor is provided. The doped region has a retrograde dopant profile such that the do...	01/07/2003
6500716	Method for fabricating high voltage transistor A method for fabricating a high voltage transistor includes the steps of: forming a plurality of drift regions on a semiconductor substrate of a first conductive type; implanting drift ions of a second conductive type into surfaces of the drift regions of...	12/31/2002
6498080	Transistor fabrication method A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underly...	12/24/2002
6495890	Field-effect transistor with multidielectric constant gate insulation layer A field-effect transistor comprises a semiconductor substrate, a gate insulation film formed selectively on the semiconductor substrate, a gate electrode formed on the gate insulation film, source/drain regions formed in surface portions of the semiconduc...	12/17/2002
6489651	MOS transistor that inhibits punchthrough A MOS transistor that includes: a semiconductor substrate; a well region formed in the semiconductor substrate, where a trench region is defined in the well region; an isolator formed on a corner of the trench region, where the trench region is filled wit...	12/03/2002
6475887	Method of manufacturing semiconductor device A semiconductor device which can effectively prevent impurity diffusion in heat treatment for electrically activating the impurity, and a manufacturing method thereof are disclosed. In the semiconductor device, a diffusion preventing layer having a depth ...	11/05/2002
6461908	Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device including a PMOS transistor (6) and an NMOS transistor (5) comprises the steps of: (a) providing a semiconductor substrate (1) having a P-well region (3), which is to be provided with the NMOS transistor (5), an...	10/08/2002
6461967	Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi...	10/08/2002
6444529	Methods of forming integrated circuitry and methods of forming elevated source/drain regions of a field effect transistor Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprisi...	09/03/2002
6432783	Method for doping a semiconductor device through a mask The manufacturing method produces a semiconductor in which current is not generated during the off state by reducing the electric field at the corner of an active region. The method includes patterning a gate material layer on a predetermined portion on t...	08/13/2002
6432830	Semiconductor fabrication process Process for treating a semiconductor substrate 25, polymeric etchant deposits 190, silicon lattice damage 195, and native silicon dioxide layers 185, are removed in sequential process steps. The polymeric etchant deposits 190 are removed using an activate...	08/13/2002
6429496	Ion-assisted oxidation methods and the resulting structures Oxidation methods, and resulting structures, comprising providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be p...	08/06/2002
6423587	Method for fabricating a MOS transistor A semiconductor wafer has a silicon substrate, at least one active area, a shallow trench isolation positioned on the silicon substrate surrounding the active area, and a first oxide layer positioned on the substrate surface within the active area. A firs...	07/23/2002
6409879	System for controlling transistor spacer width A method for controlling spacer width in a semiconductor device is provided. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness ...	06/25/2002
6410952	MOSFET with a thin gate insulating film A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4...	06/25/2002
6387803	Method for forming a silicide region on a silicon body The invented method produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented met...	05/14/2002

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Class 257/E21.433 - Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO)