Class 257/E21.43 - Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.428. This
No. of patents: 218
Last issue date: 10/14/2008

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Number	Title	Issue Date
7435657	Method of fabricating transistor including buried insulating layer and transistor fabricated using the same In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate p...	10/14/2008
7423323	Semiconductor device with raised segment A device having a raised segment, and a manufacturing method for same. An SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the insulating layer. The semiconductor material ...	09/09/2008
7414277	Memory cell having combination raised source and drain and method of fabricating same A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, w...	08/19/2008
7381623	Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second ga...	06/03/2008
7368792	MOS transistor with elevated source/drain structure In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is fo...	05/06/2008
7348232	Highly activated carbon selective epitaxial process for CMOS In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a drain region by doping a first portion and a second portion of active regions adjacent the gate, and formin...	03/25/2008
7338874	Highly integrated semiconductor device with silicide layer that secures contact margin and method of manufacturing the same Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a...	03/04/2008
7329552	Field effect transistor fabrication methods, field emission device fabrication methods, and field emission device operational methods The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a c...	02/12/2008
7312128	Selective epitaxy process with alternating gas supply In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amo...	12/25/2007
7309637	Method to enhance device performance with selective stress relief A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over ...	12/18/2007
7253060	Gate-all-around type of semiconductor device and method of fabricating the same A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mo...	08/07/2007
7253472	Method of fabricating semiconductor device employing selectivity poly deposition A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gat...	08/07/2007
7223662	Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number o...	05/29/2007
7138320	Advanced technique for forming a transistor having raised drain and source regions By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequ...	11/21/2006
7122449	Methods of fabricating semiconductor structures having epitaxially grown source and drain elements Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on...	10/17/2006
6794713	Semiconductor device and method of manufacturing the same including a dual layer raised source and drain SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration ...	09/21/2004
6703648	Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed to the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow s...	03/09/2004
6674135	Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain re...	01/06/2004
6657263	MOS transistors having dual gates and self-aligned interconnect contact windows A method of fabricating an IC device on a substrate comprising MOS transistors and other IC components. Each of the transistors of the IC device comprises a raised source electrode, a raised drain electrode, dual gate electrodes and self-aligned interconn...	12/02/2003
6652808	Methods for the electronic assembly and fabrication of devices Methods provide for electric field assisted self-assembly of functionalized programmable nucleic acids, nucleic acid modified structures, and other selective affinity or binding moieties as building blocks for: creating molecular electronic and photonic m...	11/25/2003
6645835	Semiconductor film forming method and manufacturing method for semiconductor devices thereof A method for forming a semiconductor film capable allowing easy cleaning of the processing equipment and capable of forming an epitaxial film at low temperatures as well as a manufacturing method for semiconductor devices utilizing this forming method is ...	11/11/2003
6638829	Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture A semiconductor structure and a process for its manufacture. A metal gate electrode is formed on a semiconductor substrate, the gate electrode being between nitride spacers. Lightly-doped drain regions and source/drain regions are disposed in the substrat...	10/28/2003
6638482	Reconfigurable detection and analysis apparatus and method Methods and apparatus for use of a stacked, reconfigurable system is provided. The stacked, reconfigurable system includes an inlet for receipt of a sample, a first chamber defined by a bottom support, an intermediate member, and a first spacer, the first...	10/28/2003
6635938	Semiconductor device and manufacturing method thereof A polysilicon nitride film is formed to cover a polysilicon gate. By heat treatment of the silicon nitride film in an oxygen atmosphere, a silicon oxinitride film is formed. By anisotropically etching the silicon oxinitride film and the silicon nitride fi...	10/21/2003
6624486	Method for low topography semiconductor device formation A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a p...	09/23/2003
6624036	Transistor in semiconductor device and method of manufacturing the same The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Therefore, the present invention can obtain an effect such as using a SOI substrate or a SIMOX substrate and can prevent a lowering in an electri...	09/23/2003
6624034	Method of making field effect transistor in which the increase of parasitic capacitance is restrained by scale reduction A method of producing a semiconductor device includes forming a gate electrode on a channel region on a surface of a semiconductor region of a semiconductor substrate, the channel region having a depth in the semiconductor substrate; forming a first pair ...	09/23/2003
6617654	Semiconductor device with sidewall spacers and elevated source/drain region Source and drain regions include regions of an epitaxial silicon film on the surface of the substrate and regions in the substrate. The depth of junctions of the source and drain regions is identical to or shallower than the depth of junctions of extensio...	09/09/2003
6614079	All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS A complementary metal oxide semiconductor (CMOS) device having silicide contacts that are self-aligned to deep junction edges formed within a surface of a semiconductor substrate as well as a method of manufacturing the same are disclosed. Specifically, t...	09/02/2003
6593618	MIS semiconductor device having an elevated source/drain structure In the first aspect of the invention, a semiconductor device can effectively suppress the adverse short channel effect and the possible occurrence of junction leak current and has a low resistance diffusion layer to realize a short propagation delay time ...	07/15/2003
6579770	Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled po...	06/17/2003
6563179	MOS transistor and method for producing the transistor Terminal regions of source/drain zones of an MOS transistor are configured over the substrate in the form of conductive structures, are separated from the substrate by separating layers, and exhibit a larger horizontal cross-section than doped regions for...	05/13/2003
6548875	Sub-tenth micron misfet with source and drain layers formed over source and drains, sloping away from the gate A semiconductor device having a low channel resistance without degrading transistor characteristics even for the 0.1 μm generation or later, and also: a manufacturing method of the device. The method includes fabricating source/drain electrodes and a gat...	04/15/2003
6545327	Semiconductor device having different gate insulating films with different amount of carbon A manufacturing method produces a semiconductor IC device which can maintain a low power consumption for electronic circuits and form gate-isolation layers of different thicknesses without increasing the manufacturing cost. The semiconductor IC device has...	04/08/2003
6544822	Method for fabricating MOSFET device A method for fabricating a MOSFET device having a metal gate with an ultra shallow junction and allowing the application of a self-aligned contact. A sacrificial gate is formed on a silicon substrate, as is a first silicon epitaxial layer, which is thinne...	04/08/2003
6545317	Semiconductor device having a gate electrode with a sidewall insulating film and manufacturing method thereof A gate electrode is provided via a gate insulating film formed between the source and drain regions on a semiconductor substrate, wherein the sidewall of the gate electrode excluding the exposed part formed at the upper part thereof facing the source and ...	04/08/2003
6541343	Methods of making field effect transistor structure with partially isolated source/drain junctions A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for form...	04/01/2003
6541829	Semiconductor device and method of manufacturing the same A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor regio...	04/01/2003
6518625	Semiconductor device An n-type impurity layer is formed on a boundary portion between a source/drain and a field oxide film in a portion deeper than the source/drain. Even if a metal silicide layer such as a Co silicide layer extends into a portion under the field oxide film ...	02/11/2003
6506649	Method for forming notch gate having self-aligned raised source/drain structure An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize th...	01/14/2003

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Class 257/E21.43 - Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)