Class 257/E21.429 - Using etching to form recess at gate location (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.428. This
No. of patents: 179
Last issue date: 10/28/2008

«First «Previous1 2 3 4 5 Next»Last»

Number	Title	Issue Date
7442607	Method of manufacturing transistor having recessed channel A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, deposit...	10/28/2008
7422960	Method of forming gate arrays on a partial SOI substrate The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. Th...	09/09/2008
7413969	Method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and...	08/19/2008
7393769	Transistor of a semiconductor device having a punchthrough protection layer and methods of forming the same According to some embodiments of the invention, transistors of a semiconductor device have a punchthrough protection layer, and methods of forming the same are provided. A channel-portion hole extends downward from a main surface of a semiconductor substrate. A punc...	07/01/2008
7384849	Methods of forming recessed access devices associated with semiconductor constructions The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the ...	06/10/2008
7378312	Recess gate transistor structure for use in semiconductor device and method thereof An inner spacer is formed in a sidewall of a gate in contact with a first active region that is electrically connected to an upper capacitor, thereby reducing a gate induced drain leakage (GIDL). A structure of a recess gate transistor includes a gate insulation lay...	05/27/2008
7378320	Method of forming asymmetric MOS transistor with a channel stopping region and a trench-type gate A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is...	05/27/2008
7368769	MOS transistor having a recessed gate electrode and fabrication method thereof A metal oxide semiconductor (MOS) transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes a semiconductor substrate and an isolation layer formed in a predetermined region of the semiconductor substrate ...	05/06/2008
7358144	Method for fabricating semiconductor device A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first...	04/15/2008
7354828	Semiconductor device with increased channel length and method for fabricating the same A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide lay...	04/08/2008
7354821	Methods of fabricating trench capacitors with insulating layer collars in undercut regions Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the firs...	04/08/2008
7338861	Nonvolatile memory device and method of manufacturing the same A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is...	03/04/2008
7332396	Semiconductor device with recessed trench and method of fabricating the same A semiconductor device with a recessed channel and a method of fabricating the same are provided. The semiconductor device comprises a substrate, a gate, a source, a drain, and a reverse spacer. The substrate comprises a recessed trench. The gate is formed above the...	02/19/2008
7326619	Method of manufacturing integrated circuit device including recessed channel transistor A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device iso...	02/05/2008
7314792	Method for fabricating transistor of semiconductor device A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to fo...	01/01/2008
7253060	Gate-all-around type of semiconductor device and method of fabricating the same A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mo...	08/07/2007
7163865	Method of forming transistor having recess channel in semiconductor memory, and structure thereof Embodiments of the invention include sequentially forming a pad oxide film and a mask film on a semiconductor substrate, and then forming an opening for partially exposing the pad oxide film. An undercut region is formed using the mask film as an etch mask, exposing...	01/16/2007
7148112	Method for manufacturing semiconductor device including a recess channel Disclosed is a method for manufacturing a semiconductor device. The method includes the steps of preparing a semiconductor substrate, forming a buffer oxide layer, forming a hard mask layer on the buffer oxide layer, etching an exposed portion of the buffer oxide la...	12/12/2006
7125774	Method of manufacturing transistor having recessed channel A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, deposit...	10/24/2006
6693026	Semiconductor device and method for fabricating the same A semiconductor device is disclosed, which can extend an effective channel length without changing layout. The semiconductor device includes a device barrier film formed in a semiconductor substrate, for defining an active region, a channel region formed ...	02/17/2004
6690047	MIS transistor having a large driving current and method for producing the same In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drai...	02/10/2004
6667227	Trenched gate metal oxide semiconductor device and method A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region a drain region and a channel region....	12/23/2003
6664592	Semiconductor device with groove type channel structure A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom ...	12/16/2003
6642130	Method for fabricating highly integrated transistor A method for fabricating a transistor comprises steps of forming a conductive well region, an isolation oxide layer, a first pad oxide layer, a conductive LDD (low doped drain) region and a source/drain region on a silicon substrate. A pad nitride layer i...	11/04/2003
6638825	Method for fabricating a high voltage device A high voltage device and a method for fabricating the same are disclosed, which improves voltage-resistant characteristics to protect against high voltage applied to a gate electrode. The high voltage device includes a semiconductor substrate having firs...	10/28/2003
6627488	Method for fabricating a semiconductor device using a damascene process Disclosed herein is a method of fabricating a semiconductor device using a damascene process. The method comprises the steps of: forming a dummy gate electrode on a semiconductor substrate; forming a source/drain region in the substrate; polishing and pla...	09/30/2003
6624470	Semiconductor device and a method for manufacturing same A semiconductor device, and method for manufacturing the same, manufactured by a simpler process, compared to a conventional trench lateral power MOSFET for a withstand voltage of 80 V, having a smaller device pitch and lower on-resistance per unit area a...	09/23/2003
6621118	MOSFET, semiconductor device using the same and production process therefor A MOSFET includes: a first conductivity type a semiconductor substrate having a trench formed in a surface area thereof, a gate electrode formed on the semiconductor substrate; and a trench gate electrode which is adjacent to the gate electrode and is bur...	09/16/2003
6583017	Self aligned channel implant, elevated S/D process by gate electrode damascene A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the la...	06/24/2003
6569737	Method of fabricating a transistor in a semiconductor device Forming a semiconductor transistor by embedding the gate electrode into the substrate so that a step difference between the gate electrode and the source or drain region is reduced. Device isolation areas are defined by forming at least two first trenches...	05/27/2003
6566216	Method of manufacturing a trench transistor To provide a semiconductor device and a process for manufacturing the same which is capable of suppressing short channel effect and preventing a current from leaking between a contact and a silicon substrate. The semiconductor device of the present invent...	05/20/2003
6555872	Trench gate fermi-threshold field effect transistors Field effect transistors include a semiconductor substrate of first conductivity type having a surface. A tub region of second conductivity type is in the semiconductor substrate at the surface and extends into the semiconductor substrate a first depth fr...	04/29/2003
6541317	Polysilicon doped transistor Steep concentration gradients are achieved in semiconductor device of small sizes by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates...	04/01/2003
6534370	Method for fabricating a semiconductor device having an elevated source/drain scheme The present invention is a method for fabricating a semiconductor device having an elevated source/drain scheme which includes the steps of: forming a first photoresist film on a top surface of a semiconductor substrate; forming a second photoresist film ...	03/18/2003
6528855	MOSFET having a low aspect ratio between the gate and the source/drain A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitanc...	03/04/2003
6518129	Manufacture of trench-gate semiconductor devices The manufacture of a trench-gate semiconductor device, for example a power transistor or a memory device includes the steps of forming at a surface (10a) of a semiconductor body (10) a first mask (51) having a first window (51a), providing a thin layer of...	02/11/2003
6518623	Semiconductor device having a buried-channel MOS structure A gate electrode is buried in a trench formed in the main surface of a semiconductor substrate and faces a counter doped layer, and source/drain layers are formed on both sides of the trench. Thus the source/drain layers are formed in shallower areas than...	02/11/2003
6515338	Semiconductor device and manufacturing method therefor A method of manufacturing semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a firs...	02/04/2003
6515348	Semiconductor device with FET MESA structure and vertical contact electrodes A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of ...	02/04/2003
6509609	Grooved channel schottky MOSFET A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 1017 cm-3. A grooved channel is formed in...	01/21/2003

«First «Previous1 2 3 4 5 Next»Last»

PatentStorm

Did You Know...

PatentStorm News

Class 257/E21.429 - Using etching to form recess at gate location (EPO)