Class 257/E21.428 - With a recessed gate, e.g., lateral U-MOS (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.424. This
No. of patents: 74
Last issue date: 08/12/2008

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Number	Title	Issue Date
7410873	Method of manufacturing a semiconductor device A method of forming a semiconductor device uses an anneal technique to planarize and round corners of a trench formed in a substrate. The substrate is annealed under a normal pressure in an inert atmosphere, such as an atmosphere containing one of argon, helium, and...	08/12/2008
7399663	Embedded strain layer in thin SOI transistors and a method of forming the same By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded s...	07/15/2008
7348244	Method of producing a semiconductor device A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate exte...	03/25/2008
7338862	Methods of fabricating a single transistor floating body DRAM cell having recess channel transistor structure Methods of fabricating a single transistor floating body dynamic random access memory (DRAM) cell include forming a barrier layer on a semiconductor substrate. A body layer is formed on the barrier layer. An isolation layer is formed defining a floating body region ...	03/04/2008
7319255	Semiconductor device including a metal gate electrode formed in a trench and method of forming thereof A semiconductor device including a transistor and a method of forming thereof are provided. The semiconductor device comprises a metal gate electrode. A lower portion of the metal gate electrode fills a channel trench formed at a predetermined region of a substrate,...	01/15/2008
7288828	Metal oxide semiconductor transistor device A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gat...	10/30/2007
7271068	Method of manufacture of semiconductor device A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film by...	09/18/2007
7247540	Methods of forming field effect transistors having recessed channel regions Methods of forming field effect transistors include the steps of forming a first electrically insulating layer on a semiconductor substrate having a plurality of trench isolation regions therein that define an active region therebetween. The first electrically insul...	07/24/2007
7205195	Method for fabricating NROM memory cells with trench transistors An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etch...	04/17/2007
7189617	Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the requi...	03/13/2007
7179701	Transistor with high dielectric constant gate and method for forming the same A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the...	02/20/2007
7172933	Recessed polysilicon gate structure for a strained silicon MOSFET device A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate...	02/06/2007
6693026	Semiconductor device and method for fabricating the same A semiconductor device is disclosed, which can extend an effective channel length without changing layout. The semiconductor device includes a device barrier film formed in a semiconductor substrate, for defining an active region, a channel region formed ...	02/17/2004
6656810	Semiconductor device capable of reducing dispersion in electrical characteristics and operating at high speed and method for fabricating the same There is provided a semiconductor device capable of reducing dispersion in electrical characteristics, preventing occurrence of bridge shortcircuit in a silicide process and operating at high operating speed and method for fabricating the same. In a SOI s...	12/02/2003
6624486	Method for low topography semiconductor device formation A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a p...	09/23/2003
6579765	Metal oxide semiconductor field effect transistors A method of fabricating a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device with an elevated source 29 and drain 30. A MOSFET region is defined on the surface of a silicon substrate 18, and a central area of that region removed by etching ...	06/17/2003
6573576	Semiconductor device and method for fabricating the same A semiconductor device and a method for fabricating the same is disclosed, which minimizes device degradation, minimizes noises, and simplifies the fabrication process. The device includes a substrate having a first semiconductor layer, a buried insulatin...	06/03/2003
6531410	Intrinsic dual gate oxide MOSFET using a damascene gate process Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as...	03/11/2003
6528847	Metal oxide semiconductor device having contoured channel region and elevated source and drain regions A metal oxide semiconductor (MOS) device includes a silicon substrate, source and drain regions having a predetermined junction depth (dj) relative to the surface of the silicon substrate, and a gate region having a contoured channel region for...	03/04/2003
6492696	Semiconductor device and process of manufacturing the same A semiconductor device comprises: gate electrode formed on a semiconductor substrate through the intervention of a gate insulating film; and a source/drain region provided with a silicide film on its surface and formed in the semiconductor substrate, wher...	12/10/2002
6465308	Tunable threshold voltage of a thick field oxide ESD protection device with a N-field implant A structure and a process for manufacturing semiconductor devices with improved ESD protection for high voltage applications is described. A thick field gate oxide N channel field effect transistor (FET) device with a tunable threshold voltage (Vt) is dev...	10/15/2002
6448157	Fabrication process for a semiconductor device A surface of a substrate is oxidized at a temperature equal to or higher than 1050° C., or at a oxidation speed equal to or higher than 7.5 nm/min to form an oxide film with a thickness equal to or more than 1500 nm. when the oxide film is removed, a den...	09/10/2002
6326664	Transistor with ultra shallow tip and method of fabrication A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode ...	12/04/2001
6323524	Semiconductor device having a vertical active region and method of manufacture thereof A semiconductor device and method of manufacture thereof is provided. According to one embodiment, a semiconductor device is formed by forming a trench within a substrate. An oxide layer is formed within the trench and portions of the oxide layer are remo...	11/27/2001
6316299	Formation of laterally diffused metal-oxide semiconductor device The method of the present invention comprises the following steps. First, a silicon oxide layer is formed on a semiconductor substrate. Then, a first doping N-well region is formed in the semiconductor substrate. Next, a second doping N-well region which ...	11/13/2001
6303441	Semiconductor device and method for fabricating the same A semiconductor device and a method for fabricating the same is disclosed, which minimizes device degradation, minimizes noises, and simplifies the fabrication process. The device includes a substrate having a first semiconductor layer, a buried insulatin...	10/16/2001
6285059	Structure for laterally diffused metal-oxide semiconductor A structure for forming a laterally diffused metal-oxide semiconductor is disclosed. The structure will include the following portions. They are a semiconductor layer with a conductivity type, a field insulating region into the semiconductor layer, a gate...	09/04/2001
6284609	Method to fabricate a MOSFET using selective epitaxial growth to form lightly doped source/drain regions A new method of fabricating a sub-quarter micron MOSFET device is achieved. A semiconductor substrate is provided. Isolation regions are formed in this substrate. An oxide layer is provided overlying both the substrate and the isolation regions. The oxide...	09/04/2001
6261909	Semiconductor device having ultra shallow junctions and a reduced channel length and method for making same The present invention is directed to a method of forming a transistor having very shallow junctions and a reduced channel length, and a transistor incorporating same. In general, the method comprises forming a first process layer above a semiconducting su...	07/17/2001
6246091	Lateral MOSFET having a barrier between the source/drain regions and the channel A lateral MOSFET (100) and a method for making the same. A two layer raised source/drain region (106) is located adjacent a gate structure (112). The first layer (106a) of the raised source drain is initially doped p-type and the second layer (106b) of th...	06/12/2001
6229188	MOS field effect transistor and its manufacturing method The present invention provides novel structures of MOS field effect transistor which operate with high speed and low power consumption. This has been achieved through providing epitaxial growth layers on a substrate of high impurity doping concentration i...	05/08/2001
6214670	Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance In short-channel MOSFET devices with gates constructed using conventional double-diffusing techniques, damage to the silicon substrate region near the gate structure causes hot carrier effects that degrade the device performance. The inventive process des...	04/10/2001
6207540	Method for manufacturing high performance MOSFET device with raised source and drain A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion...	03/27/2001
6194766	Integrated circuit having low voltage and high voltage devices on a common semiconductor substrate High voltage and low voltage devices are provided on a common semiconductor substrate. An integrated semiconductor circuit includes a semiconductor substrate of a first conductivity type. Well regions of a first conductivity type and well regions of a sec...	02/27/2001
6171916	Semiconductor device having buried gate electrode with silicide layer and manufacture method thereof A semiconductor device in which a salicide structure is applied to a buried gate transistor to largely reduce a difference of level or height in a element and to reduce the resistance of a gate electrode and a source/drain structure, thus enabling reliabl...	01/09/2001
6153454	Convex device with selectively doped channel In manufacturing a transistor, a doping mask is formed above a substrate. The doping mask is constructed, so that a first region of the substrate for serving as a source in the transistor and a second region of the substrate for serving as a drain in the ...	11/28/2000
6133077	Formation of high-voltage and low-voltage devices on a semiconductor substrate A high voltage transistor, formed in a bulk semiconductor material, has a gate region defined by a relatively thick field oxide and a source and drain on opposite sides of the field oxide....	10/17/2000
6130133	Fabricating method of high-voltage device The present invention provides a fabricating method of a high-voltage device. The invention provides N-- -type doped regions with properly low doping concentration in order to increase breakdown voltage. Field oxide layers are used as masks in ...	10/10/2000
6127699	Method for fabricating MOSFET having increased effective gate length A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated...	10/03/2000
6127233	Lateral MOSFET having a barrier between the source/drain regions and the channel region A lateral MOSFET (100) and a method for making the same. A two layer raised source/drain region (106) is located adjacent a gate structure (112). The first layer (106a) of the raised source drain is initially doped p-type and the second layer (106b) of th...	10/03/2000

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Class 257/E21.428 - With a recessed gate, e.g., lateral U-MOS (EPO)