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| Number | Title | Issue Date |
| 7374975 | Method of fabricating a transistor A method of forming a transistor reduces leakage current and hot carrier effects, and therefore improves current performance. The method of forming a transistor includes selectively etching the semiconductor substrate to form a substrate protrusion and expose a buri... | 05/20/2008 |
| 7351637 | Semiconductor transistors having reduced channel widths and methods of fabricating same A method of forming a channel in a semiconductor device including forming an opening in a masking layer to expose a portion of an underlying semiconductor layer through the opening is provided. The method further includes disposing a screening layer and implanting a... | 04/01/2008 |
| 7351627 | Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation fo... | 04/01/2008 |
| 7345341 | High voltage semiconductor devices and methods for fabricating the same High voltage semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device capable of high-voltage operation, comprising a substrate comprising a first well formed therein. A gate stack is formed overlying... | 03/18/2008 |
| 7344947 | Methods of performance improvement of HVMOS devices Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed wi... | 03/18/2008 |
| 7312509 | Digital temperature sensing device using temperature depending characteristic of contact resistance A digital temperature sensing device uses temperature depending characteristic of contact resistance of a MOS transistor and a self-refresh driving device adjusts its self-refresh period depending on temperature using the digital temperature sensing device. The self... | 12/25/2007 |
| 7307314 | LDMOS transistor with improved gate shield A LDMOS transistor having a gate shield provides reduced drain coupling to the gate shield and source by restricting the thickness of the gate shield and by confining a source contact to the source region without overlap of the gate. ... | 12/11/2007 |
| 7282415 | Method for making a semiconductor device with strain enhancement A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the co... | 10/16/2007 |
| 7208383 | Method of manufacturing a semiconductor component An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain e... | 04/24/2007 |
| 7163856 | Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into t... | 01/16/2007 |
| 7145196 | Asymmetric field effect transistor A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region fo... | 12/05/2006 |
| 7101764 | High-voltage transistor and fabrication process A high-voltage transistor and fabrication process in which the fabrication of the high-voltage transistor can be readily integrated into a conventional CMOS fabrication process. The high-voltage transistor of the invention includes a channel region formed beneath a ... | 09/05/2006 |
| 6703659 | Low voltage programmable and erasable flash EEPROM A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlyi... | 03/09/2004 |
| 6696734 | LDD high voltage MOS transistor A semiconductor device has a gate electrode formed on P type semiconductor substrate through a gate insulation film, a low concentration N- type drain region formed so as to be adjacent to the gate electrode, a high concentration N+ type drain region sepa... | 02/24/2004 |
| 6696727 | Field effect transistor having improved withstand voltage A transistor is protected when a high voltage is applied to a drain, without an increase in the capacitance of the drain. A semiconductor device has a gate electrode on a silicon semiconductor substrate on a gate oxide film, and a pair of N+ -t... | 02/24/2004 |
| 6693012 | Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxide MOSFETs A process for the fabrication of an integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region, and a gate oxide layer is form ... | 02/17/2004 |
| 6690060 | Field effect transistor and method of fabricating the same by controlling distribution condition of impurity region with implantation of additional ion A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide ... | 02/10/2004 |
| 6683349 | Semiconductor device and method of manufacturing the same A semiconductor device includes a gate electrode 16 on a P type well through a gate oxide film 9, a heavily-doped N+ type source layer 12 formed to be adjacent to the one end of the gate electrode 16, an N+ type drain layer 12 formed apart from the other ... | 01/27/2004 |
| 6680515 | Lateral high voltage transistor having spiral field plate and graded concentration doping A lateral high voltage transistor device is disclosed. The transistor includes a gate, a drain, and a source. The drain is located apart from the gate to form an intermediate drift region. The drift region has variable dopant concentration between the dra... | 01/20/2004 |
| 6677210 | High voltage transistors with graded extension High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region... | 01/13/2004 |
| 6670685 | Method of manufacturing and structure of semiconductor device with floating ring structure A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the drain region of the semiconductor substrate. The semiconductor... | 12/30/2003 |
| 6670252 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device which reduces the number of impurity implantations. A buffer film for reducing a quantity of an impurity implantation is provided adjacent to an MIS gate structure over a surface of a semiconductor substrat... | 12/30/2003 |
| 6667516 | RF LDMOS on partial SOI substrate In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, ... | 12/23/2003 |
| 6667512 | Asymmetric retrograde halo metal-oxide-semiconductor field-effect transistor (MOSFET) An asymmetric retrograde HALO Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) includes a semiconductor substrate. A gate is formed over the substrate, the gate defining a channel thereunder in the substrate having a source side and a drain side... | 12/23/2003 |
| 6664593 | Field effect transistor structure and method of manufacture A field effect transistor structure is formed with a body semiconductor layer (1) having source (3), channel (7), drift region (9) and drain (5). An upper metallisation layer (15, 17) is separated from the body by an oxide layer (11). The upper metallisat... | 12/16/2003 |
| 6664596 | Stacked LDD high frequency LDMOSFET A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. T... | 12/16/2003 |
| 6660602 | Stand-alone triggering structure for ESD protection of high voltage CMOS In a stand-alone snapback NMOS ESD protection structure method of manufacturing, the breakdown voltage is reduced and the structure is made more resilient to hot carrier and soft leakage degradation in the gate region by blocking the NLDD and partially bl... | 12/09/2003 |
| 6660553 | Semiconductor device having solid-state image sensor with suppressed variation in impurity concentration distribution within semiconductor substrate, and method of manufacturing the same Photolithography is used to form a photoresist (30) having an opening over an end portion of a gate structure (15) and over a region adjacent to the gate structure (15) where a photodiode (18) is to be formed. Next, using the photoresist (30) as an implan... | 12/09/2003 |
| 6660603 | Higher voltage drain extended MOS transistors with self-aligned channel and drain extensions An integrated circuit drain extension transistor. A transistor gate (72) is formed over a CMOS n-well region (10). A transistor source extension region (50), and drain extension region (52) are formed in the CMOS well region (10). A transistor region (90)... | 12/09/2003 |
| 6649976 | Semiconductor device having metal silicide film and manufacturing method thereof A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted ... | 11/18/2003 |
| 6649481 | Methods of fabricating a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned mann... | 11/18/2003 |
| 6646324 | Method and apparatus for a linearized output driver and terminator A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method fur... | 11/11/2003 |
| 6638801 | Semiconductor device and its manufacturing method A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than... | 10/28/2003 |
| 6639277 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/28/2003 |
| 6638827 | Semiconductor device and method of manufacturing it To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed... | 10/28/2003 |
| 6635925 | Semiconductor device and method of manufacturing the same A P-channel type DMOS transistor includes heavily doped source/drain layers 12 formed in an N-type well 2, a gate electrode 18 formed on a channel layer located between the source/drain layers 12, an N-type body layer 14 formed in the vicinity of the sour... | 10/21/2003 |
| 6633065 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/14/2003 |
| 6630715 | Asymmetrical MOSFET layout for high currents and high speed operation A structure and method for a field effect transistor capable of handling high currents, comprises interleaved source and drain diffusion regions with drain diffusion contacts to a first metal level over the drain diffusions only; while a second metal leve... | 10/07/2003 |
| 6624470 | Semiconductor device and a method for manufacturing same A semiconductor device, and method for manufacturing the same, manufactured by a simpler process, compared to a conventional trench lateral power MOSFET for a withstand voltage of 80 V, having a smaller device pitch and lower on-resistance per unit area a... | 09/23/2003 |
| 6620663 | Self-aligned copper plating/CMP process for RF lateral MOS device A method of fabricating an RF lateral MOS device, comprising the following steps. A substrate having a gate oxide layer formed thereover is provided. A first layer of polysilicon is formed over the gate oxide layer. A second layer of material is formed ov... | 09/16/2003 |
