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| Number | Title | Issue Date |
| 7394132 | Apparatus and methods for integrated circuit with devices with body contact and devices with electrostatic discharge protection An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contac... | 07/01/2008 |
| 7326621 | Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After formin... | 02/05/2008 |
| 7235467 | Method for forming a semiconductor device having a structure of a single crystal scandium oxide film formed on a silicon substrate A method for forming a semiconductor device includes placing a Si substrate and an Sc2O3 powder source in an oxide chamber, and vaporizing the Sc2O3 powder source in the oxide chamber so as to form a single crystal Sc... | 06/26/2007 |
| 7192834 | LDMOS device and method of fabrication of LDMOS device A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a ... | 03/20/2007 |
| 7179714 | Method of fabricating MOS transistor having fully silicided gate There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate ... | 02/20/2007 |
| 6680504 | Method for constructing a metal oxide semiconductor field effect transistor A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (... | 01/20/2004 |
| 6670694 | Semiconductor device A surface orientation other than a (100) surface orientation is exposed to the surface portion of a silicon substrate having the (100) surface orientation, for example. A silicon epitaxial growth layer is formed only on a region containing a channel formi... | 12/30/2003 |
| 6667200 | Method for forming transistor of semiconductor device A method for forming a transistor of a semiconductor device, including the step of forming channel layers of a first and a second conductive types, performing high temperature thermal process to form stabilized channel layers and forming an epitaxial chan... | 12/23/2003 |
| 6661044 | Method of manufacturing MOSEFT and structure thereof A method of manufacturing an MOSFET. A substrate is provided. A trench is formed in the substrate. A sacrificial layer is formed to fill the trench. A doped semiconductive layer is formed over the substrate. The doped semiconductive layer is patterned to ... | 12/09/2003 |
| 6656782 | Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor The source, drain and channel regions are produced in a silicon layer, completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.... | 12/02/2003 |
| 6635946 | Semiconductor device with trench isolation structure A semiconductor device with trench isolation structure is disclosed. The invention uses a trench isolation structure that can be formed by using conventional methods to prevent problems such as drain induced barrier lowering (DIBL), punch-through leakage ... | 10/21/2003 |
| 6630710 | Elevated channel MOSFET The present invention provides a semiconductor device (e.g., MOSFET) having a channel above the surface of the wafer containing a well and a junction. The elevated channel may be selectively epitaxially grown and enables higher mobility, thereby enabling ... | 10/07/2003 |
| 6624488 | Epitaxial silicon growth and usage of epitaxial gate insulator for low power, high performance devices A method for reducing off-state leakage current of a MOSFET while promoting the formation of an epitaxial gate insulator layer between the substrate and gate stack includes implanting source/drain dopant into the substrate, and then forming a very thin ep... | 09/23/2003 |
| 6624486 | Method for low topography semiconductor device formation A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a p... | 09/23/2003 |
| 6593174 | Field effect transistor having dielectrically isolated sources and drains and method for making same A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semicond... | 07/15/2003 |
| 6566734 | Semiconductor device In making a field effect transistor, a dummy gate electrode is formed before a gate electrode is formed. Extension regions, a side wall silicon nitride film, source/drain regions, a silicon oxide film, and other elements are formed with respect to the dum... | 05/20/2003 |
| 6544854 | Silicon germanium CMOS channel A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon germanium channel layer on the substrate. A gate insulation layer is formed on top of the strained silicon germanium channel layer, ... | 04/08/2003 |
| 6483148 | Self-aligned elevated transistor A method of forming a self-aligned elevated transistor using selective epitaxial growth is described. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having ... | 11/19/2002 |
| 6465332 | Method of making MOS transistor with high doping gradient under the gate The invention is directed to a method of manufacturing an area of a first type of conductivity extending a depth into a semiconductor substrate and having a doping gradient as a function of the depth into the semiconductor substrate. The method comprises ... | 10/15/2002 |
| 6429061 | Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation A strained Si CMOS structure is formed by steps which include forming a relaxed SiGe layer on a surface of a substrate; forming isolation regions and well implant regions in said relaxed SiGe layer; and forming a strained Si layer on said relaxed SiGe lay... | 08/06/2002 |
| 6420764 | Field effect transitor having dielectrically isolated sources and drains and methods for making same A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semicond... | 07/16/2002 |
| 6414361 | Buried shallow trench isolation and method for forming the same An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench ... | 07/02/2002 |
| 6406973 | Transistor in a semiconductor device and method of manufacturing the same The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective ... | 06/18/2002 |
| 6403427 | Field effect transistor having dielectrically isolated sources and drains and method for making same A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally a... | 06/11/2002 |
| 6399961 | Field effect transistor having dielectrically isolated sources and drains and method for making same A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally a... | 06/04/2002 |
| 6372563 | Self-aligned SOI device with body contact and NiSi2 gate A self-aligned SOI device with body contact and silicide gate. The SOI device is formed using an ordinary substrate such as silicon. A silicide gate is self-aligned and formed from re-crystallization of nickel and amorphous silicon. The self-aligned silic... | 04/16/2002 |
| 6368925 | Method of forming an EPI-channel in a semiconductor device An epi-channel of a uniform shape is formed by adjusting the temperature and pressure of H2 bake process to prevent the etching of a separation oxide at an interface of an active region and a field region thereby ensuring that an epi-channel is... | 04/09/2002 |
| 6362510 | Semiconductor topography having improved active device isolation and reduced dopant migration A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semicond... | 03/26/2002 |
| 6326272 | Method for forming self-aligned elevated transistor A method of forming a self-aligned elevated transistor using selective epitaxial growth is described. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having ... | 12/04/2001 |
| 6274444 | Method for forming mosfet A method for forming a MOSFET is described. The feature of this invention is that an epitaxial silicon layer with device isolation structures is formed over a substrate, wherein each device isolation structure is made of oxide. The invention need not etch... | 08/14/2001 |
| 6258677 | Method of fabricating wedge isolation transistors A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over t... | 07/10/2001 |
| 6246094 | Buried shallow trench isolation and method for forming the same An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench ... | 06/12/2001 |
| 6229188 | MOS field effect transistor and its manufacturing method The present invention provides novel structures of MOS field effect transistor which operate with high speed and low power consumption. This has been achieved through providing epitaxial growth layers on a substrate of high impurity doping concentration i... | 05/08/2001 |
| 6198114 | Field effect transistor having dielectrically isolated sources and drains and method for making same A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally a... | 03/06/2001 |
| 6190179 | Method of making a field effect transistor having a channel in an epitaxial silicon layer A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silic... | 02/20/2001 |
| 6180978 | Disposable gate/replacement gate MOSFETs for sub-0.1 micron gate length and ultra-shallow junctions A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed usi... | 01/30/2001 |
| 6174754 | Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors A method for fabricating a transistor device on a semiconductor substrate, comprising the following steps. A semiconductor substrate having a silicon surface with an overlying insulating dielectric layer is provided. The insulating dielectric layer is pat... | 01/16/2001 |
| 6147384 | Method for forming planar field effect transistors with source and drain an insulator and device constructed therefrom A method of forming a field effect transistor with source and drain on an insulator includes forming a first void region (11) in the outer surface of a semiconductor body (10) and forming a second void region (11) in the outer surface of a semiconductor b... | 11/14/2000 |
| 6143593 | Elevated channel MOSFET The present invention provides a method of producing a semiconductor device (e.g., a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) with a gate length less than 0.25 microns using standard process techniques arranged in an unstandardized proc... | 11/07/2000 |
| 6127232 | Disposable gate/replacement gate MOSFETS for sub-0.1 micron gate length and ultra-shallow junctions A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed usi... | 10/03/2000 |
