Class 257/E21.425 - With source or drain region formed by Schottky barrier or conductor-insulator-semiconductor structure (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.424. This
No. of patents: 29
Last issue date: 11/13/2007

Number	Title	Issue Date
7294898	Field effect transistor having source and/or drain forming Schottky or Schottky-like contact with strained semiconductor substrate The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effe...	11/13/2007
7202539	Semiconductor device having misfet gate electrodes with and without GE or impurity and manufacturing method thereof The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is composed of a nickel silicide film formed by reacting a silicon film doped with P, As, or Sb with an Ni fil...	04/10/2007
6680224	Methods of forming and operating field effect transistors having gate and sub-gate electrodes Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the chan...	01/20/2004
6674099	MISFET A metal insulator semiconductor field effect transistor (MISFET) is disclosed comprising a source layer being made with a material having a source band-gap (EG2) and a source mid-gap value (EGM2), the source layer having a source Fermi-Level (EF2). A drai...	01/06/2004
6648987	Method for producing nanostructures in thin films The invention relates to a method for producing a layer with a sub-micrometre structure on a substrate. First, a layer is formed on the substrate. Agents for creating elastic strains are then formed in at least one predetermined position on the layer and ...	11/18/2003
6630712	Transistor with dynamic source/drain extensions A method of fabricating an integrated circuit with a transistor having less susceptibility to off-state leakage current and short-channel effect is disclosed. The transistor includes high-K gate dielectric spacers and a T-shaped gate conductor. The high-K...	10/07/2003
6509609	Grooved channel schottky MOSFET A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 1017 cm-3. A grooved channel is formed in...	01/21/2003
6495882	Short-channel schottky-barrier MOSFET device A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket impl...	12/17/2002
6380010	Shielded channel transistor structure with embedded source/drain junctions Microelectronic structures embodying the present invention include a silicon pillar contiguous with a bulk semiconductor, the pillar being surrounded by a shallow trench isolation insulator, which has been recessed to receive polysilicon and a superjacent...	04/30/2002
6339005	Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the si...	01/15/2002
6312995	MOS transistor with assisted-gates and ultra-shallow "Psuedo" source and drain extensions for ultra-large-scale integration A MOS transistor and a method of fabricating the same for Ultra Large Scale Integration applications includes a composite gate structure. The composite gate structure is comprised of a main gate electrode and two assisted-gate electrodes disposed adjacent...	11/06/2001
6303479	Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts The present invention Is a fabrication method for a short-channel Schottky-barrier field-effect transistor device. The method of the present invention includes introducing channel dopants into a semiconductor substrate such that the dopant concentration v...	10/16/2001
6274913	Shielded channel transistor structure with embedded source/drain junctions Microelectronic structures embodying the present invention include a silicon pillar contiguous with a bulk semiconductor, the pillar being surrounded by a shallow trench isolation insulator, which has been recessed to receive polysilicon and a superjacent...	08/14/2001
6271563	MOS transistor with high-K spacer designed for ultra-large-scale integration A MOS transistor having a source and drain extension that are less than 40 nanometers in thickness to minimize the short channel effect. A gate includes a high-K dielectric spacer layer to create depletion regions in the substrate which form the drain and...	08/07/2001
6091076	Quantum WELL MOS transistor and methods for making same A new quantum well MOS transistor is described along with a processes for manufacturing it. In this transistor, the source and drain areas are separated from the channel by sufficiently thin insulating layers to enable the passage of charge carriers by th...	07/18/2000
5949103	MOSFET with tunneling insulation and fabrication method thereof A tunneling insulation film MOSFET and a fabrication method for a tunneling insulation film MOSFET avoid a short channel effect and prevent a punchthrough phenomenon by forming a tunneling insulation film between a channel area and one of source area and ...	09/07/1999
5943575	Method of forming semiconductor device A method for fabricating a semiconductor device, including the steps of providing a semiconductor substrate of a first conductivity type, defining a channel region and source/drain regions in the semiconductor substrate and etching the semiconductor subst...	08/24/1999
5840604	Methods of forming MOS transistors having hot-carrier suppression electrodes Methods of forming MOS transistors include the steps of forming hot-carrier suppression electrodes on opposing sides of an insulatedgate of a field effect transistor, to reduce hot-carrier degradation parasitics and reduce gate-to-drain overlap capacitanc...	11/24/1998
5834793	Semiconductor devices A semiconductor device has a semiconductor substrate, a source and a drain region, each formed at the surface of said semiconductor substrate, and each having a potential barrier with respect to the semiconductor substrate. A gate electrode is formed on t...	11/10/1998
5801398	Field effect transistor A field effect transistor including a gate electrode, a semiconductor region, a source electrode and a drain electrode, the source and drain electrodes being formed on opposite sides of the semiconductor region and spaced apart from the gate electrode. Th...	09/01/1998
5338698	Method of fabricating an ultra-short channel field effect transistor An ultra-short channel field effect transistor provides a combination of a shallow junction for injection of carriers into a conduction channel and a Schottky barrier below the shallow junction with a lowered barrier height to reduce the depletion region ...	08/16/1994
5177568	Tunnel injection semiconductor devices with Schottky barriers A tunnel injection type semiconductor device having an MIS structure comprising a semiconductor region, a source, a drain and a gate electrode, wherein said source and said drain are composed of a metal or metal compound member, respectively, and wherein ...	01/05/1993
5162879	Diffusionless conductor/oxide semiconductor field effect transistor and methods for making and using the same A diffusionless field effect transistor is formed at a face of a semiconductor layer (12) of a first conductivity type and includes a source conductor (36), a drain conductor (38) and a channel region (44). Source conductor (36) and drain conductor (38) a...	11/10/1992
5063171	Method of making a diffusionless virtual drain and source conductor/oxide semiconductor field effect transistor A diffusionless field effect transistor is formed at a face of a semiconductor layer (12) of a first conductivity type and includes a source conductor (36), a drain conductor (38) and a channel region (44). Source conductor (36) and drain conductor (38) a...	11/05/1991
4780429	Method of fabrication of MOS transistors having electrodes of metallic silicide In a method of fabrication of field-effect transistors having very small dimensions, the gate electrode is formed by a first layer of metallic silicide. Insulating embankments are formed along the lateral edges of the gate and a second layer of metallic s...	10/25/1988
4752815	Method of fabricating a Schottky barrier field effect transistor A method of fabricating a Schottky barrier MOSFET wherein a polysilicon gate chip is disposed adjacent the drain and source regions of a single crystal silicon substrate surface, and a metal is deposited on the top surface of the gate chip and the drain a...	06/21/1988
4696093	Fabrication of Schottky barrier MOSFETS A method for fabricating MOSFET devices by a one mask, one etch process utilizing vacuum deposited chromium, silicon upon which is grown SiO2 and an anneal process. An optional optimizing ion implantation and activating anneal step is also disc...	09/29/1987
4587710	Method of fabricating a Schottky barrier field effect transistor A method of fabricating a Schottky barrier MOSFET wherein a polysilicon gate chip is disposed adjacent the drain and source regions of a single crystal silicon substrate surface, and a metal is deposited on the top surface of the gate chip and the drain a...	05/13/1986
4432132	Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features This invention involves the defining of a submicron feature (21 or 93) in a structure, typically an insulated gate field effect transistor structure (30, 40, or 110). This feature is defined by a sidewall oxide protective masking layer (21 or 71) formed b...	02/21/1984

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Class 257/E21.425 - With source or drain region formed by Schottky barrier or conductor-insulator-semiconductor structure (EPO)