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| Number | Title | Issue Date |
| 7439121 | Dielectric film and method of forming it, semiconductor device, non-volatile semiconductor memory device, and production method for semiconductor device In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silic... | 10/21/2008 |
| 7439134 | Method for process integration of non-volatile memory cell transistors with transistors of another type A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method inc... | 10/21/2008 |
| 7425482 | Non-volatile memory device and method for fabricating the same A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer c... | 09/16/2008 |
| 7416935 | Method of manufacturing nonvolatile semiconductor memory device having adjacent selection transistors connected together A method of manufacturing a nonvolatile semiconductor memory device, including forming a gate insulating film, a first conductive layer providing floating gates and a mask, in that order, on a semiconductor substrate, forming a plurality of element-isolating regions... | 08/26/2008 |
| 7410871 | Split gate type flash memory device and method for manufacturing same A split gate type flash memory device and a method of manufacturing the split gate type flash memory device are disclosed. The split gate type flash memory device includes a silicon epitaxial layer formed in an active region of a bulk silicon substrate and a disturb... | 08/12/2008 |
| 7411243 | Nonvolatile semiconductor device and method of fabricating the same A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface... | 08/12/2008 |
| 7396722 | Memory device with reduced cell area The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk subst... | 07/08/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7387933 | EEPROM device and method of fabricating the same A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The floating junction region is formed of a second conductiv... | 06/17/2008 |
| 7374995 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposi... | 05/20/2008 |
| 7372098 | Low power flash memory devices A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and ... | 05/13/2008 |
| 7365383 | Method of forming an EPROM cell and structure therefor An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate. ... | 04/29/2008 |
| 7358558 | Flash memory device A floating gate of a flash memory device is formed in a moat formed in an isolation film. Therefore, an electric field applied between a control gate and a channel region upon cycling can be precluded or mitigated. A distance between the control gate and the channel... | 04/15/2008 |
| 7358129 | Nonvolatile semiconductor memory device and a method of the same A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, ... | 04/15/2008 |
| 7351631 | Flash memories and methods of fabricating the same The present disclosure relates to a flash memory including a common source line having a predetermined width formed on a semiconductor substrate, a common source in the semiconductor substrate below the common source line, and a couple of floating gates having a pre... | 04/01/2008 |
| 7342272 | Flash memory with recessed floating gate A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substr... | 03/11/2008 |
| 7341912 | Split gate flash memory device having self-aligned control gate and method of manufacturing the same In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor sub... | 03/11/2008 |
| 7329578 | Method of forming floating-gate tip for split-gate flash memory process A split-gate flash memory process for improving sharpness and height of a floating-gate tip has steps as follows. Using a dry etching process, a trench is formed in the first polysilicon layer through the pattern opening. An oxide layer is then deposited on the firs... | 02/12/2008 |
| 7319058 | Fabrication method of a non-volatile memory A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first ... | 01/15/2008 |
| 7315057 | Split gate non-volatile memory devices and methods of forming same Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming... | 01/01/2008 |
| 7314798 | Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the tr... | 01/01/2008 |
| 7314797 | Semiconductor device and its manufacturing method A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon o... | 01/01/2008 |
| 7312498 | Nonvolatile semiconductor memory cell and method of manufacturing the same A stacked-gate structure includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on a semiconductor substrate. The inter-electrode insulation film has a three-layer structure th... | 12/25/2007 |
| 7303956 | Flash memory cell arrays having dual control gates per memory cell charge storage element A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be couple... | 12/04/2007 |
| 7301194 | Shrinkable and highly coupled double poly EEPROM with inverter A nonvolatile EEPROM cell having a double poly arrangement provides stored data without sense amplifiers, thereby reducing power requirements. The EEPROM cell has a floating gate in a first poly layer, and a control gate overlapping the floating gate in a second pol... | 11/27/2007 |
| 7279385 | Flash memory device and manufacturing method thereof A method of manufacturing a flash memory device is provided. Multiple stack structures each comprising a tunneling oxide layer and a first conductive layer are formed over a substrate. Thereafter, multiple embedded doping regions is formed in the substrate between t... | 10/09/2007 |
| 7271065 | Horizontal memory devices with vertical gates Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do not increase the costs or complexity of the device fabrication process. The novel memory cell includes a s... | 09/18/2007 |
| 7268042 | Nonvolatile semiconductor memory and making method thereof A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then repla... | 09/11/2007 |
| 7265015 | Use of chlorine to fabricate trench dielectric in integrated circuits Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide lin... | 09/04/2007 |
| 7262096 | NAND flash memory cell row and manufacturing method thereof A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, inter-gate dielectric layer, a tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric lay... | 08/28/2007 |
| 7259051 | Method of forming SI tip by single etching process and its application for forming floating gate The invention provides a method of forming a silicon tip by a single etching process, as well as a method of forming a tip floating gate to increase erase speed. Etching gases comprising (1) chlorine and/or (2) oxygen/helium are performed to form a silicon tip witho... | 08/21/2007 |
| 7256085 | Semiconductor memory device and manufacturing method thereof A manufacturing method of a semiconductor memory device comprising the steps of: forming plural trenches in stripes in a semiconductor substrate and filling each of the trenches with an element isolation insulating film to form element isolation regions; sequentiall... | 08/14/2007 |
| 7256443 | Semiconductor memory and method of manufacturing the same A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a ... | 08/14/2007 |
| 7256091 | Method of manufacturing a semiconductor device with a self-aligned polysilicon electrode In a method of manufacturing a semiconductor device, an isolation pattern is formed on a substrate. The isolation pattern includes an opening that exposes a portion of the substrate. A preliminary polysilicon layer is formed on the substrate and the isolation patter... | 08/14/2007 |
| 7253054 | One time programmable EPROM for advanced CMOS technology A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor (100) having an increased breakdown voltage (BVdss) is disclosed. The increased breakdown voltage reduces the probability that the OTP EPROM (100) will breakdow... | 08/07/2007 |
| 7244651 | Fabrication of an OTP-EPROM having reduced leakage current The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that subs... | 07/17/2007 |
| 7238982 | Split gate type flash memory device and method for manufacturing same A split gate type flash memory device and a method of manufacturing the split gate type flash memory device are disclosed. The split gate type flash memory device includes a silicon epitaxial layer formed in an active region of a bulk silicon substrate and a disturb... | 07/03/2007 |
| 7217621 | Self-aligned split-gate NAND flash memory and fabrication process Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating... | 05/15/2007 |
| 7208796 | Split gate flash memory A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate s... | 04/24/2007 |
| 7198993 | Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI) devices A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2) is disclosed using SOI starting material (4, 6, 8) and a selective epi... | 04/03/2007 |
