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| Number | Title | Issue Date |
| 7439136 | Method of forming a layer comprising epitaxial silicon The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline ma... | 10/21/2008 |
| 7439572 | Stacked gate memory cell with erase to gate, array, and method of manufacturing A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injecton from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the fl... | 10/21/2008 |
| 7439135 | Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and exten... | 10/21/2008 |
| 7435658 | Method of manufacturing metal-oxide-semiconductor transistor A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. ... | 10/14/2008 |
| 7432134 | Semiconductor device and method of fabricating the same A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 forme... | 10/07/2008 |
| 7427547 | Three-dimensional high voltage transistor and method for manufacturing the same A method for manufacturing a three-dimensional high voltage transistor is disclosed. According to the method, lengths and widths of channels are increased while the reducing transistor forming area on plane, and semiconductor devices are completely separated from ea... | 09/23/2008 |
| 7416946 | Semiconductor device and method of manufacturing the semiconductor device A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide l... | 08/26/2008 |
| 7410844 | Device fabrication by anisotropic wet etch A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substan... | 08/12/2008 |
| 7410856 | Methods of forming vertical transistors A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming... | 08/12/2008 |
| 7405127 | Method for producing a vertical field effect transistor A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electr... | 07/29/2008 |
| 7378323 | Silicide process utilizing pre-amorphization implant and second spacer A gate electrode is formed on a substrate with a gate insulating layer therebetween. A liner is then deposited on sidewalls of the gate electrode. Source/drain extensions are implanted into the substrate. A first spacer is then formed on the liner. Deep source/drain... | 05/27/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7361558 | Method of manufacturing a closed cell trench MOSFET Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body regi... | 04/22/2008 |
| 7323373 | Method of forming a semiconductor device with decreased undercutting of semiconductor material A semiconductor device is formed by patterning a semiconductor layer to create a vertical active region and a horizontal active region, wherein the horizontal active region is adjacent the vertical active region. The semiconductor layer overlies an insulating layer.... | 01/29/2008 |
| 7319060 | Semiconductor device and method of manufacturing the semiconductor device A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gat... | 01/15/2008 |
| 7276754 | Annular gate and technique for fabricating an annular gate A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surfac... | 10/02/2007 |
| 7276416 | Method of forming a vertical transistor The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline ma... | 10/02/2007 |
| 7271048 | Method for manufacturing trench MOSFET A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is f... | 09/18/2007 |
| 7268032 | Termination for trench MIS device having implanted drain-drift region A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drai... | 09/11/2007 |
| 7262099 | Methods of forming field effect transistors A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided laterally between the mass of material and the semiconductive material. The space comprises an outermost port... | 08/28/2007 |
| 7241649 | FinFET body contact structure A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface... | 07/10/2007 |
| 7183164 | Methods of reducing floating body effect Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a prefe... | 02/27/2007 |
| 7087950 | Flash memory cell, flash memory device and manufacturing method thereof The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said ch... | 08/08/2006 |
| 6680232 | Trench etch with incremental oxygen flow A method for forming trenches in a device layer disposed on a silicon semiconductor substrate comprises: covering the device layer with an etch resistant masking layer to define at least two trench regions; removing semiconductor material from the exposed... | 01/20/2004 |
| 6674139 | Inverse T-gate structure using damascene processing A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the ce... | 01/06/2004 |
| 6674099 | MISFET A metal insulator semiconductor field effect transistor (MISFET) is disclosed comprising a source layer being made with a material having a source band-gap (EG2) and a source mid-gap value (EGM2), the source layer having a source Fermi-Level (EF2). A drai... | 01/06/2004 |
| 6664806 | Memory address and decode circuits with ultra thin body transistors A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. The decoder includes a number of vertical pillars extending outwardly from ... | 12/16/2003 |
| 6664143 | Methods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls Vertical field effect transistors are fabricated by depositing a vertical channel on a microelectronic substrate at a thickness along the microelectronic substrate that is independent of lithography, the vertical channel extending orthogonal to the microe... | 12/16/2003 |
| 6660590 | Vertical transistor and method of manufacturing thereof The present invention discloses a vertical transistor wherein source/drain regions are formed by using a self-alignment method without using a latest photolithography, channels are formed via a selective epitaxial growth (hereinafter, referred to as `SEG`... | 12/09/2003 |
| 6642575 | MOS transistor with vertical columnar structure A field-effect transistor has a vertical columnar structure to restrain a short channel effect without impairing the operating speed of an element. In a semiconductor device having a field-effect transistor with a vertical columnar structure, an n-type di... | 11/04/2003 |
| 6639268 | Flash memory with ultra thin vertical body transistors Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating gate transistor includes a pillar extending outwardly from... | 10/28/2003 |
| 6632712 | Method of fabricating variable length vertical transistors A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the comp... | 10/14/2003 |
| 6624032 | Structure and process flow for fabrication of dual gate floating body integrated MOS transistors A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer... | 09/23/2003 |
| 6605860 | Semiconductor structures and manufacturing methods A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallograph... | 08/12/2003 |
| 6589821 | Methods of forming thin film transistors A method of forming a thin film transistor over a substrate is provided whereby at least one of the source region or the drain region is conductively doped while preventing conductivity doping of the channel region without any masking of the channel regio... | 07/08/2003 |
| 6521935 | Mos transistor and dram cell configuration A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection... | 02/18/2003 |
| 6518622 | Vertical replacement gate (VRG) MOSFET with a conductive layer adjacent a source/drain region and method of manufacture therefor The present invention provides a VRG structure formed on a semiconductor wafer substrate. The VRG structure has a first source/drain region located in a semiconductor wafer substrate, and a conductive layer located adjacent the source/drain region, a seco... | 02/11/2003 |
| 6511884 | Method to form and/or isolate vertical transistors A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on eith... | 01/28/2003 |
| 6506638 | Vertical double gate transistor structure A method of manufacturing a vertical transistor. The vertical transistor utilizes a deposited amorphous silicon layer to form a source region. The vertical gate transistor includes a double gate structure for providing increased drive current. A wafer bon... | 01/14/2003 |
| 6492232 | Method of manufacturing vertical semiconductor device An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently change... | 12/10/2002 |
